Patents by Inventor Yuuichi Takeuchi
Yuuichi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8604540Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.Type: GrantFiled: November 30, 2010Date of Patent: December 10, 2013Assignee: DENSO CORPORATIONInventors: Rajesh Kumar Malhan, Naohiro Sugiyama, Yuuichi Takeuchi
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Patent number: 8575648Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.Type: GrantFiled: December 22, 2010Date of Patent: November 5, 2013Assignee: DENSO CORPORATIONInventors: Yuuichi Takeuchi, Rajesh Kumar Malhan, Naohiro Sugiyama
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Publication number: 20130105889Abstract: A method for manufacturing a switching device, which includes a trench type gate electrode and first to fourth semiconductor regions, is provided. The first semiconductor region is in contact with a gate insulating film and is of n-type. The second semiconductor region is in contact with the gate insulating film, and is of p-type. The third semiconductor region is in contact with the gate insulating film, and is of n-type. The fourth semiconductor region is a p-type semiconductor region which is positioned in a range deeper than the second semiconductor region and consecutive with the second semiconductor region, and which faces the gate insulating film via the third semiconductor region. The manufacturing method includes forming the second semiconductor region in which aluminum is doped, and implanting boron into a range in which the fourth semiconductor region is to be formed in the semiconductor substrate.Type: ApplicationFiled: September 14, 2012Publication date: May 2, 2013Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu FUJIWARA, Hisashi ISHIMABUSHI, Yukihiko WATANABE, Narumasa SOEJIMA, Toshimasa YAMAMOTO, Yuuichi TAKEUCHI
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Patent number: 8274086Abstract: A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.Type: GrantFiled: July 28, 2009Date of Patent: September 25, 2012Assignees: DENSO CORPORATION, University of CambridgeInventors: Rajesh Kumar Malhan, Yuuichi Takeuchi, Jeremy Rashid
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Patent number: 7989231Abstract: In a method of manufacturing a silicon carbide semiconductor device, a trench and a thickness measurement section are formed in a surface of a semiconductor substrate made of silicon carbide. The thickness measurement section includes a plurality of grooves and a protruding portion provided between the grooves so as to have a predetermined width. When an epitaxial layer made of silicon carbide is grown, a thickness of the epitaxial layer formed on the surface of the semiconductor substrate is measured by calculating a difference in height between a surface of the epitaxial layer formed on a portion of the surface of the semiconductor substrate different from the thickness measurement section and a top surface of the protruding portion. The predetermined width is less than a surface migration amount of atoms during growth of the epitaxial layer.Type: GrantFiled: March 11, 2010Date of Patent: August 2, 2011Assignee: DENSO CORPORATIONInventors: Atsuya Akiba, Yuuichi Takeuchi
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Publication number: 20110156054Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Applicant: DENSO CORPORATIONInventors: Yuuichi TAKEUCHI, Rajesh Kumar Malhan, Naohiro Sugiyama
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Publication number: 20110156052Abstract: A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.Type: ApplicationFiled: December 16, 2010Publication date: June 30, 2011Applicant: DENSO CORPORATIONInventors: Rajesh Kumar Malhan, Yuuichi Takeuchi, Naohiro Sugiyama
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Publication number: 20110133211Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.Type: ApplicationFiled: November 30, 2010Publication date: June 9, 2011Applicant: DENSO CORPORATIONInventors: Rajesh Kumar MALHAN, Naohiro Sugiyama, Yuuichi Takeuchi
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Patent number: 7825449Abstract: An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n?-type drift layer to extend into the n?-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.Type: GrantFiled: October 30, 2008Date of Patent: November 2, 2010Assignee: DENSO CORPORATIONInventors: Naohiro Suzuki, Yuuichi Takeuchi, Takeshi Endo, Eiichi Okuno, Toshimasa Yamamoto
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Publication number: 20100233832Abstract: In a method of manufacturing a silicon carbide semiconductor device, a trench and a thickness measurement section are formed in a surface of a semiconductor substrate made of silicon carbide. The thickness measurement section includes a plurality of grooves and a protruding portion provided between the grooves so as to have a predetermined width. When an epitaxial layer made of silicon carbide is grown, a thickness of the epitaxial layer formed on the surface of the semiconductor substrate is measured by calculating a difference in height between a surface of the epitaxial layer formed on a portion of the surface of the semiconductor substrate different from the thickness measurement section and a top surface of the protruding portion. The predetermined width is less than a surface migration amount of atoms during growth of the epitaxial layer.Type: ApplicationFiled: March 11, 2010Publication date: September 16, 2010Applicant: DENSO CORPORATIONInventors: Atsuya Akiba, Yuuichi Takeuchi
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Patent number: 7763543Abstract: A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.Type: GrantFiled: October 28, 2008Date of Patent: July 27, 2010Assignee: DENSO CORPORATIONInventors: Masatake Nagaya, Yuuichi Takeuchi, Katsuhiro Nagata
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Publication number: 20100025693Abstract: A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.Type: ApplicationFiled: July 28, 2009Publication date: February 4, 2010Applicants: DENSO CORPORATION, University of CambridgeInventors: Rajesh Kumar Malhan, Yuuichi Takeuchi, Jeremy Rashid
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Publication number: 20090124060Abstract: A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.Type: ApplicationFiled: October 28, 2008Publication date: May 14, 2009Applicant: DENSO CORPORATIONInventors: Masatake Nagaya, Yuuichi Takeuchi, Katsuhiro Nagata
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Publication number: 20090114969Abstract: An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n?-type drift layer to extend into the n?-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.Type: ApplicationFiled: October 30, 2008Publication date: May 7, 2009Applicant: DENSO CORPORATIONInventors: Naohiro Suzuki, Yuuichi Takeuchi, Takeshi Endo, Eiichi Okuno, Toshimasa Yamamoto
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Patent number: 7241694Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.Type: GrantFiled: April 14, 2005Date of Patent: July 10, 2007Assignee: DENSO CorporationInventors: Yuuichi Takeuchi, Rajesh Kumar Malhan, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20060273323Abstract: A semiconductor device includes: a SiC substrate; a silicide layer disposed on the SiC substrate; and a carbide layer disposed on the silicide layer. The silicide layer includes a first metal, and the carbide layer includes a second metal. The first metal is Ni or Ni alloy, and the second metal is Ti, Ta or W. The device provides excellent ohmic contact and high quality surface metallization construction.Type: ApplicationFiled: June 7, 2006Publication date: December 7, 2006Applicants: DENSO CORPORATION, The University of Newcastle upon TyneInventors: Takeo Yamamoto, Malhan Kumar, Yuuichi Takeuchi, Konstantin Vassilevski, Nicholas Wright
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Patent number: 7078329Abstract: An insulating film (2) is formed on a semiconductor substrate (1) formed of silicon carbide. A contact hole (3) is formed in the insulating film (2) to expose a part of the upper surface of the semiconductor substrate (1). Then, nickel (Ni) (4?) is formed above the semiconductor substrate (1). Subsequently, the semiconductor substrate (1) is subjected to a heat treatment, whereby the contact portion of nickel (4?) chemically bonds with the semiconductor substrate (1) to become an alloy layer (4) of silicon carbide and nickel. Nickel (4?) on the insulating film (2) is selectively removed by etching liquid for dissolving the nickel.Type: GrantFiled: April 15, 2004Date of Patent: July 18, 2006Assignee: Denso CorporationInventors: Takeshi Endou, Yuuichi Takeuchi
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Publication number: 20050233539Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.Type: ApplicationFiled: April 14, 2005Publication date: October 20, 2005Inventors: Yuuichi Takeuchi, Rajesh Malhan, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 6853006Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.Type: GrantFiled: July 31, 2003Date of Patent: February 8, 2005Assignee: Denso CorporationInventors: Mitsuhiro Kataoka, Yuuichi Takeuchi, Masami Naito, Rajesh Kumar, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: RE43840Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.Type: GrantFiled: October 21, 2010Date of Patent: December 4, 2012Assignee: DENSO CORPORATIONInventors: Mitsuhiro Kataoka, Yuuichi Takeuchi, Masami Naito, Rajesh Kumar, Hiroyuki Matsunami, Tsunenobu Kimoto