Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Abstract: A system includes a host device, a hardware offload engine, and a non-volatile storage to store on-disk data. The hardware offload engine is represented to the host device as being a storage having a virtual storage capacity, and the host device transmits an offload command to the hardware offload engine as a data write command without requiring kernel changes or special drivers.

Abstract: Machine learning, artificial intelligence, and other computer-implemented methods are used to identify various semantically important chunks in documents, automatically label them with appropriate datatypes and semantic roles, and use this enhanced information to assist authors and to support downstream processes. Chunk locations, datatypes, and semantic roles can often be automatically determined from what is here called “context”, to wit, the combination of their formatting, structure, and content; those of adjacent or nearby content; overall patterns of occurrence in a document, and similarities of all these things across documents (mainly but not exclusively among documents in the same document set).

Abstract: Disclosed herein are systems (e.g., moving bed redox systems) and methods for supplying thermal energy to an endothermic chemical process.

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Abstract: An electrical connection terminal includes a welding part welded to a solder pad of a battery pack cell to be electrically connected to the battery pack cell, a press fitting part pressed into a hole on a battery pack signal acquisition board to be electrically connected to the battery pack signal acquisition board, and an elastic part connected between the welding part and the press fitting part. The press fitting part is elastically floated in a length direction of the electrical connection terminal relative to the welding part.

Abstract: The present disclosure describes techniques of metadata management for transparent block level compression. A first area may be created in a backend solid state drive. The first area may comprise a plurality of entries. The plurality of entries may be indexed by addresses of a plurality of blocks of uncompressed data. Each of the plurality of entries comprises a first part configured to store metadata and a second part configured to store compressed data. Each of the plurality blocks of uncompressed data may be compressed individually to generate a plurality of compressed blocks. Metadata and at least a portion of compressed data associated with each of the plurality of compressed blocks may be stored in one of the plurality of entries based on an address of a corresponding block of uncompressed data. A second area may be created in the backend solid state drive for storing the rest of the compressed data.

Abstract: A 10G rate OLT terminal transceiver integrated chip based on XGSPON and DFB laser includes: a burst mode receiver RX which amplifies an optical signal from each ONU client into an electrical signal through a burst transimpedance amplifier TIA, processes amplitude detection, and outputs the signal whose amplitude met the threshold requirements to a host, and comprises a fast recovery module to discharge charges in an AC coupling capacitor to achieve multi-packet transmission without mutual interference, thereby meeting the timing sequence requirement of the XGSPON protocol; a continuous mode transmitter TX which receives the electrical signal attenuated by a PCB board, and selects a bypass BYPASS path or a clock data recovery CDR path for activation according to a degree of attenuation; and a digital control unit DIGIITAL which communicates with the host and provides control signals for the burst mode receiver RX and the continuous mode transmitter TX.

Abstract: A DFB laser DC-coupled output power configuration scheme with adjustable voltage difference. utilizes an external or internal power configuration unit to provide two electric DC power supplies with a fixed voltage difference for the transmitting unit TX of the DFB laser and the optical transceiver integrated chip, and at the same time optimizes the transmitting unit TX. The optimization scheme is that: the transistors in the transmitting unit TX are all low-voltage high-speed tubes, the transmitting unit TX includes a negative capacitance structure composed of capacitors C1 and C2, serving as an auxiliary structure for improving bandwidth. After optimization, the minimum voltage of the power supply voltage port TVCC of the transmitting unit TX is 2.7V and the problems that the output eye diagram is severely cracked and cannot be used when the traditional DFB laser configuration scheme with an external 3.3V power supply is tested at high temperature are solved.

Abstract: A DFB laser DC-coupled output power configuration scheme belongs to the field of laser drivers in optical communication integrated circuits. The present invention solves the existing problems in the conventional DFB laser power supply configuration scheme. The power configuration scheme of the present invention utilizes an external or internal power configuration unit to provide two electric DC power supplies with a fixed voltage difference for the transmitting unit TX of the DFB laser and the optical transceiver integrated chip, and at the same time optimizes the transmitting unit TX. The optimization scheme is that: the transistors in the transmitting unit TX are all low-voltage high-speed tubes, the transmitting unit TX includes a negative capacitance structure composed of capacitors C1 and C2, serving as an auxiliary structure for improving bandwidth. After optimization, the minimum voltage of the power supply voltage port TVCC of the transmitting unit TX is 2.7V.

Abstract: A 10G rate OLT terminal transceiver integrated chip based on XGPON and EML laser includes: a burst mode receiver RX which amplifies an electrical signal originated each ONU client and processed through a burst mode receiver TIA, processes amplitude and frequency double-detection, and outputs the signal whose amplitude and waveform pulse width met the threshold requirements to a host, and comprises a fast recovery module to meet the timing sequence requirement of the XGPON protocol; a continuous mode transmitter TX which receives the electrical signal attenuated by a PCB board, and selects a bypass BYPASS path or a clock data recovery CDR path according to a degree of attenuation to drive the EML laser; a digital control unit DIGIITAL which provides control signals to the burst mode receiver RX and the continuous mode transmitter TX; and a power module POWER to supply working power to the chip.

Abstract: A 10G rate OLT terminal transceiver integrated chip based on EPON with EML laser includes: a burst mode receiver RX which processes signal amplification and selects one of the two preset channels as a working channel for output through receiving an external command from a host; a continuous mode transmitter TX which receives the electrical signal attenuated by a PCB board, and selects a bypass BYPASS path or a clock data recovery CDR path according to a degree of attenuation to drive the EML laser; a digital control unit DIGIITAL for path selection of the burst mode receiver RX; and a power module POWER, wherein the opening and closing of the two rate channels are controlled by the level judgment unit and the output blocking unit.

Abstract: A 10G rate OLT terminal transceiver integrated chip based on XGSPON and DFB laser includes: a burst mode receiver RX which amplifies an optical signal from each ONU client into an electrical signal through a burst transimpedance amplifier TIA, processes amplitude detection, and outputs the signal whose amplitude met the threshold requirements to a host, and comprises a fast recovery module to discharge charges in an AC coupling capacitor to achieve multi-packet transmission without mutual interference, thereby meeting the timing sequence requirement of the XGSPON protocol; a continuous mode transmitter TX which receives the electrical signal attenuated by a PCB board, and selects a bypass BYPASS path or a clock data recovery CDR path for activation according to a degree of attenuation; and a digital control unit DIGIITAL which communicates with the host and provides control signals for the burst mode receiver RX and the continuous mode transmitter TX.

Abstract: A 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser includes: a burst mode receiver RX which processes amplitude detection, and outputs the signal whose amplitude and waveform pulse width met the threshold requirements to a host, and comprises a fast recovery module to discharge charges in an AC coupling capacitor to achieve multi-packet transmission without mutual interference and to meet the timing sequence requirement of the XGSPON protocol; a continuous mode transmitter TX which receives the electrical signal attenuated by a PCB board, and selects a bypass BYPASS path or a clock data recovery CDR path according to a degree of attenuation to drive the EML laser; a digital control unit DIGIITAL which communicates with the host and provides control signals to the burst mode receiver RX and the continuous mode transmitter TX; and a power module POWER.

Abstract: A 10G rate OLT terminal transceiver integrated chip based on XGPON and DFB laser includes: a burst mode receiver RX, a continuous mode transmitter TX and a digital control unit DIGIITAL. The burst mode receiver RX amplifies an optical signal from each ONU client into an electrical signal through a burst TIA, processes double-detection for amplitude and frequency of the electrical signal, outputs the signal whose amplitude and waveform pulse width meet the threshold requirements to the host, and uses a fast recovery module to control the timing to meet the XGPON protocol. The continuous mode transmitter TX receives the electrical signal attenuated by the PCB, and selects the bypass BYPASS path or the clock data recovery CDR path according to the degree of attenuation. The digital control unit DIGIITAL is used to provide control signals for the burst mode receiver RX and the continuous mode transmitter TX.

Abstract: A DFB laser DC-coupled output power configuration scheme belongs to the field of laser drivers in optical communication integrated circuits. The present invention solves the existing problems in the conventional DFB laser power supply configuration scheme. The power configuration scheme of the present invention utilizes an external or internal power configuration unit to provide two electric DC power supplies with a fixed voltage difference for the transmitting unit TX of the DFB laser and the optical transceiver integrated chip, and at the same time optimizes the transmitting unit TX. The optimization scheme is that: the transistors in the transmitting unit TX are all low-voltage high-speed tubes, the transmitting unit TX includes a negative capacitance structure composed of capacitors C1 and C2, serving as an auxiliary structure for improving bandwidth. After optimization, the minimum voltage of the power supply voltage port TVCC of the transmitting unit TX is 2.7V.

Abstract: A high-speed optical transceiver integrated chip drive circuit with phase delay compensation function includes a transmitting end drive circuit to drive the laser to emit light to transmit signals and a receiving end drive circuit to optimize the signal degradation caused by the signal sent by the transmitting end drive circuit to the laser via the transmission backplane; a long code phase lead adjustment circuit is arranged on the main channel of the transmitting end drive circuit, and a long code phase lag adjustment circuit is set on the main channel of the receiving end drive circuit. The present invention is used to optimize high-speed signals and solve the problem that the CML drive circuit at the receiving end or the laser drive circuit at the transmitting end cannot compensate the difference between the group delay and phase delay for the high-speed signal after passing through the backplane (Laser device).

Abstract: A high-speed optical transceiver integrated chip drive circuit with phase delay compensation function includes a transmitting end drive circuit to drive the laser to emit light to transmit signals and a receiving end drive circuit to optimize the signal degradation caused by the signal sent by the transmitting end drive circuit to the laser via the transmission backplane; a long code phase lead adjustment circuit is arranged on the main channel of the transmitting end drive circuit, and a long code phase lag adjustment circuit is set on the main channel of the receiving end drive circuit. The present invention is used to optimize high-speed signals and solve the problem that the CML drive circuit at the receiving end or the laser drive circuit at the transmitting end cannot compensate the difference between the group delay and phase delay for the high-speed signal after passing through the backplane (Laser device).

Abstract: A receiving and sending integrated chip for an OLT, which relates to the field of integrated circuits and optical communications. The present invention arms at resolving the problem of high production costs and long production cycle due to the fact that the functions of a limiting amplifier and a laser driver of a traditional OLT end optical module based on a GPON and an EPON are implemented by means of two circuit chips. The present invention provides two solutions. The first solution is designed based on the EPON, a transmitter threshold value configuration mode is that the threshold value configuration is implemented after an upper computer and a slave I2C circuit in the chip cooperate to complete electrifying, and LOS signal determination in a receiver can be automatically reset by means of a chip internal module.

Abstract: A receiving and sending integrated chip for an OLT, which relates to the field of integrated circuits and optical communications. The present invention arms at resolving the problem of high production costs and long production cycle due to the fact that the functions of a limiting amplifier and a laser driver of a traditional OLT end optical module based on a GPON and an EPON are implemented by means of two circuit chips. The present invention provides two solutions. The first solution is designed based on the EPON, a transmitter threshold value configuration mode is that the threshold value configuration is implemented after an upper computer and a slave I02C circuit in the chip cooperate to complete electrifying, and LOS signal determination in a receiver can be automatically reset by means of a chip internal module.