Abstract: A receiving and sending integrated chip for an OLT, which relates to the field of integrated circuits and optical communications. The present invention arms at resolving the problem of high production costs and long production cycle due to the fact that the functions of a limiting amplifier and a laser driver of a traditional OLT end optical module based on a GPON and an EPON are implemented by means of two circuit chips. The present invention provides two solutions. The first solution is designed based on the EPON, a transmitter threshold value configuration mode is that the threshold value configuration is implemented after an upper computer and a slave I2C circuit in the chip cooperate to complete electrifying, and LOS signal determination in a receiver can be automatically reset by means of a chip internal module.

Abstract: A receiving and sending integrated chip for an OLT, which relates to the field of integrated circuits and optical communications. The present invention arms at resolving the problem of high production costs and long production cycle due to the fact that the functions of a limiting amplifier and a laser driver of a traditional OLT end optical module based on a GPON and an EPON are implemented by means of two circuit chips. The present invention provides two solutions. The first solution is designed based on the EPON, a transmitter threshold value configuration mode is that the threshold value configuration is implemented after an upper computer and a slave I02C circuit in the chip cooperate to complete electrifying, and LOS signal determination in a receiver can be automatically reset by means of a chip internal module.

Abstract: Electron emitters and methods of fabricating the electron emitters are disclosed. According to certain embodiments, an electron emitter includes a tip with a planar region having a diameter in a range of approximately (0.05-10) micrometers. The electron emitter tip is configured to release field emission electrons. The electron emitter further includes a work-function-lowering material coated on the tip.

Abstract: Provided is an apparatus and method for detecting body parts, the method including identifying a group of sub-images relevant to a body part in an image to be detected, assigning a reliability coefficient for the body part to the sub-images in the group of sub-images based on a basic vision feature of the sub-images and an extension feature of the sub-images to neighboring regions, and detecting a location of the body part by overlaying sub-images having reliability coefficients higher than a threshold value.

Abstract: Provided is an apparatus and method for detecting body parts, the method including identifying a group of sub-images relevant to a body part in an image to be detected, assigning a reliability coefficient for the body part to the sub-images in the group of sub-images based on a basic vision feature of the sub-images and an extension feature of the sub-images to neighboring regions, and detecting a location of the body part by overlaying sub-images having reliability coefficients higher than a threshold value.

Abstract: A structure and method for an improved a bond pad structure. A top wiring layer and a top dielectric (IMD) layer over a semiconductor structure are provided. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. A buffer opening is formed in the buffer dielectric layer exposing at least of portion of the top wiring layer. A barrier layer is formed over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. The conductive buffer layer is planarized to form a buffer pad in the buffer opening. A passivation layer is formed over the buffer pad and the buffer dielectric layer. A bond pad opening is formed in the passivation layer over at least a portion of the buffer pad. A bond pad support layer is formed over the buffer pad and the buffer dielectric layer. A bond pad layer is formed over the bond pad support layer.

Abstract: A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in the buffer dielectric layer exposing at least of portion of the top wiring layer. We form a barrier layer over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. We planarize the conductive buffer layer to form a buffer pad in the buffer opening. We form a passivation layer over the buffer pad and the buffer dielectric layer. We form a bond pad opening in the passivation layer over at least a portion of the buffer pad. We form a bond pad support layer over the buffer pad and the buffer dielectric layer. We form a bond pad layer over the a bond pad support layer.

Abstract: A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in the buffer dielectric layer exposing at least of portion of the top wiring layer. We form a barrier layer over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. We planarize the conductive buffer layer to form a buffer pad in the buffer opening. We form a passivation layer over the buffer pad and the buffer dielectric layer. We form a bond pad opening in the passivation layer over at least a portion of the buffer pad. We form a bond pad support layer over the buffer pad and the buffer dielectric layer. We form a bond pad layer over the a bond pad support layer.

Abstract: A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in the buffer dielectric layer exposing at least of portion of the top wiring layer. We form a barrier layer over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. We planarize the conductive buffer layer to form a buffer pad in the buffer opening. We form a passivation layer over the buffer pad and the buffer dielectric layer. We form a bond pad opening in the passivation layer over at least a portion of the buffer pad. We form a bond pad support layer over the buffer pad and the buffer dielectric layer. We form a bond pad layer over the a bond pad support layer.