Abstract: A battery charger integrated circuit with temperature control is disclosed that includes a temperature sensor circuit and a charging current generator circuit. Upon receiving a temperature reading voltage (VDT), the temperature sensing circuit is operable to generate a second reference voltage (VREF) that is a function of the first reference voltage (VREF1). The charging current generator circuit generates and continuously adjusts a reference current (I1) and a charging current (IOUT) according to the second reference voltage (VREF). Whenever the temperature reading voltage (VDT) exceeds the first reference voltage, the temperature sensor circuit is operable to adjust the second reference voltage (VREF).

Abstract: A battery charger integrated circuit with temperature control is disclosed that includes a temperature sensor circuit and a charging current generator circuit. Upon receiving a temperature reading voltage (VDT), the temperature sensing circuit is operable to generate a second reference voltage (VREF) that is a function of the first reference voltage (VREF1). The charging current generator circuit generates and continuously adjusts a reference current (I1) and a charging current (IOUT) according to the second reference voltage (VREF). Whenever the temperature reading voltage (VDT) exceeds the first reference voltage, the temperature sensor circuit is operable to adjust the second reference voltage (VREF).

Abstract: A battery charger integrated circuit with temperature control is disclosed that includes a temperature sensor circuit and a charging current generator circuit. Upon receiving a temperature reading voltage (VDT), the temperature sensing circuit is operable to generate a second reference voltage (VREF) that is a function of the first reference voltage (VREF1). The charging current generator circuit generates and continuously adjusts a reference current (I1) and a charging current (IOUT) according to the second reference voltage (VREF). Whenever the temperature reading voltage (VDT) exceeds the first reference voltage, the temperature sensor circuit is operable to adjust the second reference voltage (VREF).

Abstract: Methods and apparatus are disclosed for protecting circuits from damages caused by elevated temperatures. Presented embodiments illustrate IC thermal protection circuits that shut down power delivery circuits when the circuit temperature reaches a predefined upper threshold and restart the circuit when the circuit cools down to a predefined lower threshold. Other embodiments provide soft shutdown and soft restart, where not only the temperature range between the shutdown and the restart is predetermined, but also the time between the start of a shutdown process and the complete shutdown is controllable.

Abstract: A battery charging circuit monitors the IC temperature through monitoring the charging die temperature, or directly monitoring the IC temperature using a temperature sensor. A maximum temperature allowed for the charging die is predetermined. The charging circuit is capable of reducing charging current at the predetermined maximum temperature value. The charging die signal is compared by a reference signal to achieve the reduction of charging current at the maximum allowed temperature value.

Abstract: Methods and apparatus are disclosed for protecting circuits from damages caused by elevated temperatures. Presented embodiments illustrate IC thermal protection circuits that shut down power delivery circuits when the circuit temperature reaches a predefined upper threshold and restart the circuit when the circuit cools down to a predefined lower threshold. Other embodiments provide soft shutdown and soft restart, where not only the temperature range between the shutdown and the restart is predetermined, but also the time between the start of a shutdown process and the complete shutdown is controllable.

Abstract: A single capacitor (C) can be used for both readout and noise reduction in an imaging sensor. This dual-purpose use of the single capacitor is facilitated by a switching arrangement (?1-?5) which connects the capacitor to a low impedance node (n7, n41) during charge storage. The low impedance node is also used to drive a column readout line (Vout).

Abstract: A mixed-signal integrated circuit (12) having compensation for leakage through an ESD cell (16) at an external terminal of a reference voltage is disclosed. A reference voltage generator circuit (14) generates a reference voltage that is low-pass filtered by an on-chip resistor (Rf) and an off-chip capacitor (Coc). The ESD cell (16) is connected at the terminal node between the resistor (Rf) and the capacitor (Coc), as is an ESD compensation circuit (20, 20′, 20″). The ESD compensation circuit (20, 20′, 20″) includes a dummy ESD cell (29) that is physically matched to the ESD cell (16), and a current mirror biased in a direction corresponding to the direction of the expected leakage through ESD cell (16). The ESD compensation circuit (20, 20′, 20″) ensures that very little of the leakage current through ESD cell (16) is conducted by the filter resistor (Rf), so that changes in this leakage current over temperature or bias conditions does not modulate the reference voltage.

Abstract: A single capacitor (C) can be used for both readout and noise reduction in an imaging sensor. This dual-purpose use of the single capacitor is facilitated by a switching arrangement (&PHgr;1-&PHgr;5) which connects the capacitor to a low impedance node (n7, n41) during charge storage. The low impedance node is also used to drive a column readout line (Vout).

Abstract: A low-pass filter circuit includes: a first compound transistor device (22) and (24) coupled between an input node (30) and an output node (32); a first transistor (20) coupled to the input node (30), a gate of the first transistor (20) is coupled to a drain of the first transistor (20); a second compound transistor device (36) and (38) coupled between a gate of the first compound transistor device (22) and (24) and the gate of the first transistor (20); a second transistor (34) coupled to the first transistor (20) and having a gate coupled to a gate of the second compound transistor device (36) and (38), the gate of the second transistor (34) is coupled to a drain of the second transistor (34); a current source (26) coupled to the drain of the second transistor (34); a first capacitor (C1) coupled to the output node (32); and a second capacitor (C2) coupled to the gate of the first compound transistor device (22) and (24).

Abstract: A method and circuitry for amplifying an input signal. First, second and third input signals are provided with the third input signal being the average of the first and second input signals. A ramp signal is provided using the third input signal as the ramp base signal and the first and second signals are compared with said ramp signal to provide an output responsive to only one of the first and second signals when the ramp signal and one of the first and second signals are equivalent. A load is driven in response to the output. In addition, an error signal can be provided by comparing the output with the first and second input signals and altering the first and second input signals as a result of comparing the output with the first and second input signals. The output is a function of the value of the ramp signal when the ramp signal and one of said first and second signals are equivalent.

Abstract: A resistive element including a P-channel MOS device (101, 401, 402, 608a-608c) having a first and second current carrying electrodes, and a gate. The first current carrying electrode forms a first impedance terminal and the second current carrying electrode forms a second impedance terminal. A bias circuit (103, 104, 105, 106) coupled to the first current carrying electrode and gate of the P-channel MOS device (101, 401, 402, 608a-608c). The bias circuit (103, 104, 105, 106) generates a voltage less than the threshold voltage of the P-channel MOS device (101, 401, 402, 608a-608c).