Abstract: A self-testing transceiver comprises a receiver, and a transmitter including a power amplifier (PA) and a plurality of transmitter pre-PA stages. The plurality of transmitter pre-PA stages are configured to generate a communication signal at a receive frequency of the transceiver and the receiver is configured to process another communication signal at a transmit frequency of the transceiver, thereby enabling transceiver self-testing. A method for use by a transceiver for self-testing comprises generating a first communication signal at a transmit frequency of the transceiver by a transmitter of the transceiver, processing the first communication signal by a receiver of the transceiver, generating a second communication signal at a receive frequency of the transceiver by the transmitter, and processing the second communication signal by the receiver. The described generating and processing of the first and second communication signals resulting in self-testing by the transceiver.

Abstract: A self-testing transceiver comprises a receiver, and a transmitter including a power amplifier (PA) and a plurality of transmitter pre-PA stages. The plurality of transmitter pre-PA stages are configured to generate a communication signal at a receive frequency of the transceiver and the receiver is configured to process another communication signal at a transmit frequency of the transceiver, thereby enabling transceiver self-testing. A method for use by a transceiver for self-testing comprises generating a first communication signal at a transmit frequency of the transceiver by a transmitter of the transceiver, processing the first communication signal by a receiver of the transceiver, generating a second communication signal at a receive frequency of the transceiver by the transmitter, and processing the second communication signal by the receiver. The described generating and processing of the first and second communication signals resulting in self-testing by the transceiver.

Abstract: A frequency tuning device for use in a crystal oscillator circuit includes a first fine tuning array of capacitors, a second fine tuning array of capacitors and a coarse tuning array of capacitors coupled in parallel to produce a tuning capacitance for tuning the crystal oscillator. The first fine tuning array of capacitors includes a binary weighted switched capacitor network, the second fine tuning array of capacitors includes a thermometer coded switched capacitor network and the coarse tuning array of capacitors includes a binary weighted switched capacitor network with a different unit capacitance value than the first and second fine tuning arrays.

Abstract: A frequency tuning device for use in a crystal oscillator circuit includes a first fine tuning array of capacitors, a second fine tuning array of capacitors and a coarse tuning array of capacitors coupled in parallel to produce a tuning capacitance for tuning the crystal oscillator. The first fine tuning array of capacitors includes a binary weighted switched capacitor network, the second fine tuning array of capacitors includes a thermometer coded switched capacitor network and the coarse tuning array of capacitors includes a binary weighted switched capacitor network with a different unit capacitance value than the first and second fine tuning arrays.

Abstract: An imager that is better suited for low-light detection capability. In accordance with a preferred embodiment, the imager may be easily configured to provide an imager having multi-resolution capability where SNR can be adjusted for optimum low-level detectibility. Multi-resolution signal processing functionality is provided on-chip to achieve high speed imaging, as well as low power consumption. The imager architecture employs an improved pixel binning approach with fully differential circuits situated so that all extraneous and pick-up noise is eliminated. The current implementation requires no frame transfer memory, thereby reducing chip size. The reduction in area enables larger area format light adaptive imager implementations.

Abstract: An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Abstract: An improved image sensing array including a semiconductive substrate having formed therein an array of discrete substrate areas organized in rows and columns. The array of areas is segmented into a plurality of blocks, each including a sub-array of the areas. At least one of the rows of each block has at least one reader cell formed therein, and the remaining rows of the block have photosensor cells formed in each area thereof. Each column of each block forms a column block including a plurality of photosensor cells, and a node line communicatively coupling each photosensor cell of the column block to an associated reader cell. A row address line is coupled to each photosensor cell in a particular row of the array. A column bit line is coupled to each reader cell in a particular column of the array. A block select line is coupled to each reader cell in a particular row of the array containing reader cells.

Abstract: An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Abstract: An active pixel sensing structure includes an array of pixel unit cells each of which an adapted to alternate between a light sensing mode wherein the cell outputs an image signal and a reset mode wherein the cell outputs a reset signal. The image signal is proportional to light incident on the cell, and the reset signal is proportional to a predefined reference potential. An improved readout circuit according to the present invention includes a first sample and hold component for receiving and storing the image signal, and second sample and hold component for receiving and storing the reset signal. A signal amplifier is provided for each sample and hold component. A switching circuit is operable between a first mode and a second mode. In the second mode, the first and second sample and hold components are operatively decoupled from the corresponding signal amplifiers while input terminals of the signal amplifiers are connected to a source of predetermined reference potential.

Abstract: An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Abstract: An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Abstract: A capacitively-coupled successive approximation analog-to-digital converter utilizes a capacitively coupled multiplying digital to analog converter to generate a succession of voltages which are compared to the input voltage to be digitized. The capacitively coupled multiplying digital to analog converter generates the required succession of analog voltage levels utilizing very low power in response to digital signals. A double-sided version of the invention processes differential inputs with improved common-non-ideality mode rejection.

Abstract: An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes charge integrating amplifiers in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.