Abstract: The present disclosure relates to the technical field of pyrolysis and improvement of caking middling coals, in particular to a low temperature pyrolysis method of a caking middling coal. The present disclosure provides a low temperature pyrolysis method of a caking middling coal, including the following steps: conveying the caking middling coal into a pyrolysis reactor through a top of the pyrolysis reactor; dividing a reaction chamber of the pyrolysis reactor into a drying section, a softening section, a melting and depolymerization section, a solidification section, and a cooling section by means of multi-channel gas distribution; and conducting zoned temperature control-based pyrolysis to obtain semi-coke at a bottom of the reactor as well as tar and coal gas at the top of the reactor. The pyrolysis method can well avoid caking and swelling of the caking middling coal during pyrolysis.

Abstract: The present disclosure provides an arctigenin liquid nano-preparation and a preparation method thereof, and relates to the technical field of pharmaceutical preparation. In the present disclosure, arctigenin is prepared into a liquid nano-preparation, having advantages of distribution of a droplet diameter on nanoscale, significantly increased specific surface area, rapid absorption, and high bioavailability. Meanwhile, nano-preparation entered the body can be captured by wandering leucocytes, and a medicament is delivered to inflammatory lesions through chemiotaxis, thereby conferring a targeted drug delivery feature on the arctigenin and making a therapy more targeted. Moreover, in the present disclosure, the arctigenin is dissolved in an oil phase, and the oil phase is dissolved in water by emulsification to further make the arctigenin dissolve in the water and increase water solubility of the arctigenin.

Abstract: The present disclosure relates to the technical field of pyrolysis and improvement of caking middling coals, in particular to a low temperature pyrolysis method of a caking middling coal. The present disclosure provides a low temperature pyrolysis method of a caking middling coal, including the following steps: conveying the caking middling coal into a pyrolysis reactor through a top of the pyrolysis reactor; dividing a reaction chamber of the pyrolysis reactor into a drying section, a softening section, a melting and depolymerization section, a solidification section, and a cooling section by means of multi-channel gas distribution; and conducting zoned temperature control-based pyrolysis to obtain semi-coke at a bottom of the reactor as well as tar and coal gas at the top of the reactor. The pyrolysis method can well avoid caking and swelling of the caking middling coal during pyrolysis.

Abstract: The present disclosure describes aspects of a conductive receptacle collar for desense mitigation. In aspects, an apparatus comprises a printed circuit board assembly (PCBA) that includes an integrated circuit with signal lines for a wired data interface. The apparatus also includes a coupling component with a receptacle for the wired data interface and an enclosure in which the PCBA is mounted. The enclosure has an opening through which the receptacle for the wired data interface is exposed. A conductive collar is disposed between an exterior surface of the receptacle and an interior surface of this opening. The conductive collar contacts the receptacle's exterior surface and the interior surface of the opening to electrically couple these respective surfaces. By so doing, the conductive collar improves grounding of the receptacle to the enclosure, which may mitigate the desense of the apparatus's wireless receivers caused by operation of the wired data interface.

Abstract: The present disclosure describes aspects of a conductive receptacle collar for desense mitigation. In aspects, an apparatus comprises a printed circuit board assembly (PCBA) that includes an integrated circuit with signal lines for a wired data interface. The apparatus also includes a coupling component with a receptacle for the wired data interface and an enclosure in which the PCBA is mounted. The enclosure has an opening through which the receptacle for the wired data interface is exposed. A conductive collar is disposed between an exterior surface of the receptacle and an interior surface of this opening. The conductive collar contacts the receptacle's exterior surface and the interior surface of the opening to electrically couple these respective surfaces. By so doing, the conductive collar improves grounding of the receptacle to the enclosure, which may mitigate the desense of the apparatus's wireless receivers caused by operation of the wired data interface.

Abstract: An electrical connector can include a tongue, a shell, multiple pins, and a shield. The shell can enclose the tongue, and can define an aperture for receiving a plug. The multiple pins can extend along the tongue. The multiple pins can extend beyond the shell a first distance from a back portion of the shell. The back portion of the shell can be opposite from the aperture. The shield can extend from a back portion of the shell. The shield can include a first arm extending away from the back portion of the shell a second distance and a second arm extending from the first arm. The second distance can be greater than the first distance.

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.

Abstract: Methods and apparatus for equalization of a high speed serial bus. A well-tuned passive equalization circuit for use with high frequency differential signals suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: Possible outcomes can be determined by combining simulation methods on a pool of input variables. Certain members of the pool are identified as members of a first set of variables (e.g., priority set), and certain other members of the pool of input variables are identified as members of a second set of variables (e.g., non-priority set). A first set of possible values for the first set of variables can be generated by applying a first simulation method. A second set of possible values for the second set of variables can be generated by applying a second simulation method that differs from the first simulation method in various ways, such as accuracy, completion time, and computational expense. A copula data structure can be used to maintain correlations between the variables of the pool of input variables when generating a hybrid set of simulated values based on the first and second simulation.

Abstract: Methods and apparatus for equalization of a high speed serial bus. Various aspects of the present disclosure are directed to a well-tuned passive equalization circuit for use with high frequency differential signals that suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

Abstract: An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract: An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.