Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract: Apparatus described herein include ear warmer frames. In some embodiments, an apparatus includes a frame configured to be disposed about a portion of a head of a user. The frame includes a first member and a second member. The first member has a first portion and a second portion. The first portion of the first member has a cross-sectional profile, and the second portion of the first member has a cross-sectional profile smaller than the cross-sectional profile of the first portion of the first member. An end portion of the second member has a cross-sectional profile substantially corresponding to the cross-sectional profile of the first portion of the first member. The second member defines an opening configured to receive the second portion of the first member such that when the frame is in a collapsed configuration an abutment interface is defined, and surfaces of the abutment interface are substantially continuous between the first member and the second member.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: A capacitive fingerprint sensor that may be formed of an array of sensing elements. Each capacitive sensing element of the array may register a voltage that varies with the capacitance of a capacitive coupling. A finger may capacitively couple to the individual capacitive sensing elements of the sensor, such that the sensor may sense a capacitance between each capacitive sensing element and the flesh of the fingerprint. The capacitance signal may be detected by sensing the change in voltage on the capacitive sensing element as the relative voltage between the finger and the sensing chip is changed. Alternately, the capacitance signal may be detected by sensing the change in charge received by the capacitive sensing elements as the relative voltage between the finger and the sensing chip is changed.

Abstract: Memory systems and methods for creating the same are disclosed. The memory systems can include pairs of IC packages mounted on either side of a system substrate. Contacts formed on the IC packages can be communicatively coupled with contacts of a paired IC package using vias that extend through the system substrate. The IC packages can further communicate with a controller mounted on one side of the system substrate using the vias as well as conductive traces formed in the system substrate.

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract: A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads.

Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract: Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.

Abstract: A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads.

Abstract: Computer-implemented systems and methods are provided for generating a simulated forecast based on members of a pool of input risk factor variables. Certain members of the pool of input risk factor variables are identified as members of a first set of variables, and certain other members of the pool of input risk factor variables are identified as members of a second set of variables. A first simulation is generated via a first simulation method using the first set of variables, and a second simulation is generated via a second simulation method that differs from the first simulation method using the second set of variables. The first simulation and the second simulation are generated using correlations among variables in the first set of variables and variables in the second set of variables.

Abstract: Computer-implemented systems and methods are provided for implementing a dynamic model switching simulator that generates a plurality of simulations. A system and method generates a simulation comprising predictions over a plurality of time periods. Generating a simulation includes generating a first time period prediction using a first model of a first model type. Generating the plurality of subsequent time period predictions includes evaluating the model switching rule to identify whether to switch models for a subsequent time period prediction, generating the subsequent time period prediction using the first model if a switch of models is not identified, and generating the subsequent time period prediction using a second model of a second model type otherwise.

Abstract: A computerized system simulates a non-linear Decision Feedback Equalizer. The computerized system includes a user interface, an output port, and a controller coupled to the user interface and to the output port. The controller is configured to (i) receive electronic design automation commands from a user through the user interface, (ii) generate, as an electronic model of the non-linear Decision Feedback Equalizer, an electronic representation of a linear filter in response to the electronic design automation commands, and (iii) integrate the electronic representation of the linear filter into an electronic circuit design having other electronic representations of other electronic circuits. The electronic circuit design is externally accessible through the output port.

Abstract: An area array device has a grid array of primary electrical contacts coupled to a coupling surface of the device and configured to carry data signals between the area array package and a circuit board. The area array device also has an additional series of secondary electrical contacts coupled to the coupling surface of the device and configured to carry power signals between the area array package and the circuit board. The additional series of secondary electrical contacts provides a relatively large amount of power to the area array package while allowing a manufacturer to maintain the number of primary electrical contacts of the grid array configured to carrying data signals and therefore maintain the overall performance of the area array package.

Abstract: An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase adjustment circuit on the receiver compensates for the phase differences. Clock jitter and skew is reduced and the number of IDDQ pins is reduced to provide a more effective design and high density package.

Abstract: A circuit board module has an IC device, discrete components, and a circuit board structure in electrical communication with the IC device and the discrete component. The circuit board structure includes non-conductive material defining a top surface of the circuit board structure and a bottom surface of the circuit board structure, vias supported by the non-conductive material, top pads electrically coupled to the vias, and bottom pads electrically coupled to the vias. The top pads are disposed along the top surface of the circuit board structure and are soldered to IC device. The bottom pads are disposed along the bottom surface of the circuit board structure and are configured to solder to the discrete components. The bottom pads include a group of angled bottom pads which is soldered to a group of the discrete components substantially at 45 degree angles relative to sides of the IC device.

Abstract: An area array device has a grid array of primary electrical contacts coupled to a coupling surface of the device and configured to carry data signals between the area array package and a circuit board. The area array device also has an additional series of secondary electrical contacts coupled to the coupling surface of the device and configured to carry power signals between the area array package and the circuit board. The additional series of secondary electrical contacts provides a relatively large amount of power to the area array package while allowing a manufacturer to maintain the number of primary electrical contacts of the grid array configured to carrying data signals and therefore maintain the overall performance of the area array package.

Abstract: A circuit board has a first component interface configured to connect to a first circuit board component, a second component interface configured to connect to a second circuit board component, a differential signal pair electrically connecting the first component interface to the second component interface, and a signal return path configured to operate as a signal return pathway for the differential signal pair. The signal return path includes first conductive material which is in electrical communication with the first component interface, second conductive material which is in electrical communication with the second component interface, and a dielectric which provides direct current separation between the first and second conductive material. Such a circuit board may alleviate the need for DC blocking capacitors along the differential pair, and along other differential pairs when the circuit board has multiple differential pairs connecting the first and second component interfaces.

Abstract: A circuit board component includes a substrate having non-conductive material and conductive material supported by the non-conductive material. The conductive material defines a circuit board interface, a die interface, a heat spreader interface, and (iv) a set of connections which interconnects the circuit board interface, the die interface and the heat spreader interface. The component further includes a die coupled to the die interface. The die includes integrated circuitry which is configured to electrically communicate with a circuit board when the circuit board couples to the circuit board interface. The component further includes a heat spreader coupled to the heat spreader interface. The heat spreader is configured to dissipate heat from the die. The heat spreader in combination with the heat spreader interface forms an electromagnetic interference shield when a portion of the circuit board interface connects to a ground reference of the circuit board.

Abstract: A circuit board has a first component interface configured to connect to a first circuit board component, a second component interface configured to connect to a second circuit board component, a differential signal pair electrically connecting the first component interface to the second component interface, and a signal return path configured to operate as a signal return pathway for the differential signal pair. The signal return path includes first conductive material which is in electrical communication with the first component interface, second conductive material which is in electrical communication with the second component interface, and a dielectric which provides direct current separation between the first and second conductive material. Such a circuit board may alleviate the need for DC blocking capacitors along the differential pair, and along other differential pairs when the circuit board has multiple differential pairs connecting the first and second component interfaces.