Abstract: The present disclosure relates to a compound of formula (I) or a pharmaceutically acceptable salt thereof. The present disclosure further relates to methods of inhibiting viral replication including contacting one or more cells that have been infected with a virus with an effective amount of a compound of formula (I) or a pharmaceutically acceptable salt thereof, wherein the virus comprises a flavivirus. Also disclosed is a method of treating and/or preventing a flavivirus infection and/or a condition resulting from a flavivirus infection including administering an effective amount of a compound of formula (I) or a pharmaceutically acceptable salt thereof under conditions effective to treat and/or prevent a flavivirus infection and/or a condition resulting from a flavivirus infection.

Abstract: Provided herein are antibodies including antigen-binding fragments thereof that specifically recognizing Pseudomonas Psl. Also provided are methods of making and using these antibodies.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: The present application provides antibodies including antigen-binding fragments thereof that specifically recognizing Complement component 5a (C5a). Also provided are methods of making and using these antibodies.

Abstract: The present disclosure relates to a Prp8 intein splicing inhibitor. The present disclosure further relates to a method of treating and/or preventing a fungal infection, said method comprising administering a Prp8 intein splicing inhibitor under conditions effective to treat and/or prevent a fungal infection. Also disclosed is a method of inhibiting Prp8 intein expression or activity in a cell or tissue, said method comprising administering a compound under conditions effective to inhibit Prp8 intein expression or activity in a cell or tissue. Further disclosed are methods for screening for compounds that inhibit Prp8 intein splicing comprising an assay and a kit for predicting the likelihood of Prp8 inhibition.

Abstract: A multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

Abstract: The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

Abstract: The present application provides a method for manufacturing a semiconductor device including a merged active area (AA). The method includes forming a fuse gate structure over the active area; forming a device gate structure over the active area and adjacent to the fuse gate structure; and forming a contact plug coupled to the active area and extending away from the substrate. The fuse gate structure and the device gate structure are parallel and are formed over the active area.

Abstract: A transient current planning method for an ultra-high-speed permanent magnet synchronous motor for improving speed regulation response capabilities is provided. A transient current planning module uses a voltage model considering transient current changes to calculate current instruction values of an ultra-high-speed permanent magnet synchronous motor under MTPA control, general flux-weakening control, and MTPV control; a mode switching condition judgment subsystem judges whether a control mode is MTPA control or general flux-weakening control, or MTPV control, and sends d- and q-axis current instruction values in the corresponding control mode to a voltage decoupling control module; and the voltage decoupling control module calculates d- and q-axis voltage instruction values for controlling the motor, so as to realize control over the ultra-high-speed permanent magnet synchronous motor.

Abstract: A method and a system of lithium battery state of charge (SOC) estimation based on second-order difference particle filtering belonging to the technical field of battery management are provided. The method includes the following steps: building a second-order RC battery model of a lithium battery; performing model parameterization by using a least squares algorithm with a forgetting factor; and generating an importance density function through a second-order central difference Kalman filtering (SCDKF) algorithm, improving a particle filtering algorithm to obtain a second-order difference particle filtering (SCDPF) algorithm, and performing SOC estimation on a lithium battery by using the SCDPF. The estimation method provided by the disclosure is accurate and has greater estimation accuracy than an unscented particle filtering algorithm (UPF), an unscented Kalman filtering algorithm (UKF), and an extended Kalman filtering algorithm (EKF). An SOC value of the lithium battery may thus be accurately estimated.

Abstract: A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

Abstract: Provided is a method of inhibiting viral replication, including contacting one or more cells that has been infected or contacted with a flavivirus with an effective amount of niclosamide, temoporfin, nitazoxanide, tizoxanide, erythrosin B, methylene blue. Contacting one or more cells that have been infected with a flavivirus may include administering the compound to a mammal, a human, or other subject. The flavivirus may be Dengue virus serotype 1, Dengue virus serotype 2, Dengue virus serotype 3, Dengue virus serotype 4, yellow fever virus, West Nile virus, Zika virus, Japanese encephalitis virus, tick-born encephalitis virus, Powassan virus, St. Louis encephalitis virus, or other flavivirus.

Abstract: A double-layer coiled tubing double-gradient drilling system, on the basis of conventional drilling equipment, includes a double-layer coiled tubing system, spacer fluid, a downhole lifting pump system, throttling control systems and a data monitoring system. Power fluid enters an annular space of the tubing through an adapter, passes through a downhole lifting pump, enters an inner pipe through a bridge channel, and enters the bottom hole through the drill bit. Return fluid enters an annular channel of the tubing through a recovery hole, then enters the inner pipe through the bridge channel and enters the lifting pump, and then enters a solid control system through the adapter and the control systems in sequence. Gradient control of the bottom hole pressure is realized through monitoring of the spacer fluid and control of the drilling pump unit and throttling control systems. The problem of narrow safe drilling density window is solved.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

Abstract: The present application provides an anti-fuse one-time programmable (OTP) memory array and a manufacturing method of the anti-fuse one-time programmable (OTP) memory array. The memory array includes: active areas; pairs of programming word lines and read word lines; and dummy word lines. The active areas extend along a first direction in a semiconductor substrate, and are separately arranged along a second direction. The programming word lines, the read word lines and the dummy word lines extend along the second direction over the semiconductor substrate. A region in which a pair of programming word line and read word line are intersected with one of the active areas defines a unit cell in the memory array. The dummy word lines respectively lie between adjacent pairs of programming word lines and read word lines. A region in which one of the dummy word lines is intersected with one of the active areas defines an isolation transistor.

Abstract: A method for a robot to simulate the passive mechanical state of human limb muscles, comprising a method for simulating different degrees of tensile force in bending the elbow or bending the knee in the human body, and a method for simulating different degrees of tensile force in extending the elbow or extending the knee in the human body. The robot is provided with, sequentially connected, a base (1), a shoulder joint assembly, an upper arm (5), an elbow joint assembly, a forearm (14), and a palm (16). The shoulder joint assembly is able to drive the upper arm (5) to rotate in all directions, and the elbow joint assembly is able to drive the forearm (14) to bend or extend.

Abstract: A method and a system for identifying third-order model parameters of a lithium battery based on a likelihood function are provided, which relates to a method for estimating battery model parameters of a lithium battery under different temperatures, different system-on-chips (SOCs), and charge-discharge currents. The method includes the following steps. A third-order battery model of the lithium battery is established. A battery model output voltage Ud and a total battery current I under different temperatures, different SOCs, and charge-discharge currents are collected. The likelihood function is adopted to construct an identification model, and the collected data is substituted into the identification model to calculate the battery model parameters. Identified parameters are substituted into the third-order battery model to obtain a battery terminal voltage to be compared with a measured terminal voltage.