Patents by Inventor Zhongjian Teng

Zhongjian Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10944049
    Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang
  • Publication number: 20210055659
    Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng
  • Patent number: 10854809
    Abstract: An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tom Zhong, Jesmin Haq, Zhongjian Teng
  • Patent number: 10831104
    Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng
  • Publication number: 20200343444
    Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Yi Yang, Zhongjian Teng, Yu-Jen Wang
  • Publication number: 20200303636
    Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10714679
    Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Zhongjian Teng, Yu-Jen Wang
  • Patent number: 10680168
    Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Publication number: 20200142313
    Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng
  • Publication number: 20200075844
    Abstract: A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Publication number: 20200075847
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Yi Yang, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10520818
    Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng
  • Patent number: 10475991
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness ?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10475987
    Abstract: A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Publication number: 20190341542
    Abstract: A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Publication number: 20190312197
    Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 10, 2019
    Inventors: Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Publication number: 20190259941
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Inventors: Yi Yang, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Publication number: 20190245141
    Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 8, 2019
    Inventors: Yi Yang, Zhongjian Teng, Yu-Jen Wang
  • Publication number: 20190207083
    Abstract: An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Tom Zhong, Jesmin Haq, Zhongjian Teng
  • Publication number: 20190148630
    Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang