Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A hard mask layer is provided on the MTJ stack. The hard mask layer is patterned to form a hard mask. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on sidewalls of the MTJ device. The sidewall damage is removed by applying a CMP slurry which physically attacks and removes the sidewall damage on the MTJ device.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A hard mask layer is provided on the MTJ stack. The hard mask layer is patterned to form a hard mask. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on sidewalls of the MTJ device. The sidewall damage is removed by applying a CMP slurry which physically attacks and removes the sidewall damage on the MTJ device.

Abstract: A process flow for forming a magnetic tunnel junction (MTJ) cell that is self-aligned to an underlying bottom electrode (BE) is disclosed. The BE is comprised of a lower BE layer having a first width (w1), and an upper (second) BE layer with a second width (w2) where w2>w1. Preferably, the BE has a T shape. A stack of MTJ layers including an uppermost hard mask is deposited on the BE and has width w2 because of a self-aligned deposition process. A dummy MTJ stack is also formed around the first BE layer. An ion beam etch where ions are at an incident angle <90° with respect to the substrate is used to remove extraneous material on the sidewall. Thereafter, an encapsulation layer is deposited to insulate the MTJ cell, and to fill a gap between the first BE layer and dummy MTJ stack.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A bottom electrode layer is provided on a substrate. A seed layer is deposited on the bottom electrode layer. The seed layer and bottom electrode layer are patterned. A dielectric layer is deposited over the patterned seed layer and bottom electrode layer and planarized wherein the seed layer is exposed. Thereafter, a stack of MTJ layers is deposited on the patterned seed layer comprising a pinned layer, a tunnel barrier layer, and a free layer. The MTJ stack is then patterned to form a MTJ device. Because the seed layer was patterned before the MTJ patterning step, the exposure of the device to etching plasma gases is shortened and thus, etch damage is minimized.

Abstract: A CMOS device is provided in a substrate. A magnetic tunnel junction (MTJ) is provided over the CMOS device and connected to the CMOS device by a metal ring contact wherein a dielectric or other filling material forms the center of the metal ring contact and wherein a bottom of the metal ring contact underlying said filling material is metal.