Abstract: A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed ring data bus apparatus with a plurality of nodes, and associated application apparatus in data communication with at least one of the nodes. A synchronous ring protocol is used to transfer data packets or frames around the ring data bus, so as to avoid data collisions. The packets or frames include both payload and control data, and may be addressed to higher layer processes of the application apparatus. In one variant, differentially signaled optical or electrical bus segments are utilized to interface with the nodes, and data is serialized before transmission on the ring data bus. In another variant, a common clock signal is transmitted around the ring with the data packets or frames.

Abstract: A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed ring data bus apparatus with a plurality of nodes, and associated application apparatus in data communication with at least one of the nodes. A synchronous ring protocol is used to transfer data packets or frames around the ring data bus, so as to avoid data collisions. The packets or frames include both payload and control data, and may be addressed to higher layer processes of the application apparatus. In one variant, differentially signaled optical or electrical bus segments are utilized to interface with the nodes, and data is serialized before transmission on the ring data bus. In another variant, a common clock signal is transmitted around the ring with the data packets or frames.

Abstract: A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed data bus apparatus; a user interface apparatus in data communication with the high-speed data bus apparatus configured to enable a user to interact with the computerized apparatus; an input/output apparatus in data communication with the high-speed data bus apparatus and configured to interchange data with one or more devices external to the computerized apparatus; a mass storage apparatus in data communication with the high-speed data bus apparatus and configured to store data; a computer program for use by the high-speed data bus apparatus; and a substantially unified data interface in data communication with each of the user interface apparatus, the input/output apparatus, the mass storage apparatus, and the high-speed data bus apparatus.

Abstract: A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed data bus apparatus; a user interface apparatus in data communication with the high-speed data bus apparatus configured to enable a user to interact with the computerized apparatus; an input/output apparatus in data communication with the high-speed data bus apparatus and configured to interchange data with one or more devices external to the computerized apparatus; a mass storage apparatus in data communication with the high-speed data bus apparatus and configured to store data; a computer program for use by the high-speed data bus apparatus; and a substantially unified data interface in data communication with each of the user interface apparatus, the input/output apparatus, the mass storage apparatus, and the high-speed data bus apparatus.

Abstract: A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed data bus apparatus; a user interface apparatus in data communication with the high-speed data bus apparatus configured to enable a user to interact with the computerized apparatus; an input/output apparatus in data communication with the high-speed data bus apparatus and configured to interchange data with one or more devices external to the computerized apparatus; a mass storage apparatus in data communication with the high-speed data bus apparatus and configured to store data; a computer program for use by the high-speed data bus apparatus; and a substantially unified data interface in data communication with each of the user interface apparatus, the input/output apparatus, the mass storage apparatus, and the high-speed data bus apparatus.

Abstract: A computerized apparatus configured for high-speed data transactions between components thereof In one embodiment, the computerized apparatus includes a high-speed data bus apparatus; a user interface apparatus in data communication with the high-speed data bus apparatus configured to enable a user to interact with the computerized apparatus; an input/output apparatus in data communication with the high-speed data bus apparatus and configured to interchange data with one or more devices external to the computerized apparatus; a mass storage apparatus in data communication with the high-speed data bus apparatus and configured to store data; a computer program for use by the high-speed data bus apparatus; and a substantially unified data interface in data communication with each of the user interface apparatus, the input/output apparatus, the mass storage apparatus, and the high-speed data bus apparatus.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.

Abstract: A signal presence detection device has a first reference voltage generation device in the form of a first voltage divider, a second reference voltage generation device in the form of a second voltage divider and a third reference voltage generation device in the form of a third voltage divider. The detection device also has a signal conditioning device such as a hysteretic amplifier with an output that is coupled to the first and second voltage dividers. A comparison device is coupled to all three voltage dividers to compare a voltage of the first voltage divider to a voltage of the third voltage divider and to compare a voltage of the second voltage divider to the voltage of the third voltage divider. The comparison device is coupled at two outputs thereof to two respective inputs of an XOR device. The XOR device receives respective signals from the first and second outputs of the comparison device and produces a signal presence output that serves to indicate whether an incoming signal is present or absent.

Abstract: A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status portion has an independent status parity bit. The status parity bit is recalculated and updated whenever a status bit in the entry is changed. In another embodiment, each status bit is provided with a corresponding shadow status bit. Each status bit and its corresponding shadow status bit is always loaded with the same data. In this manner, every change 1-bit change to a status bit is made as two identical 1-bit changes to the status bit and its corresponding shadow status bit. The two identical 1-bit changes are parity neutral, thereby permitting status changes without requiring recomputing and saving a new parity.

Abstract: An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.