Abstract: A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the event of a non-match, the new data can be written to the invalid locations in a single clock cycle.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if there are multiple matching entries, in some instances only one matching entry has its counter incremented. The counter value can be written or read as part of either the least significant or most significant bits of the CAM entry.

Abstract: The present invention provides a large capacity distributed content addressable memory (CAM) made up of a plurality of smaller CAMs interconnected on a high speed data bus. Each of the smaller CAMs is located at a local node on the data bus and configured to receive commands originating from both the local node in which the CAM is located and a local node in which another CAM on the data bus is located. As the resources and the data being stored by all the CAMs are shared through the high speed data bus, the aggregate contents of all the CAMs can be viewed as being stored in a single virtual CAM.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A system and method for validating a memory device using a Gray Code is described. The system and method tests data segments of a memory storage location concurrently, where a data segment may be a nibble. Each data segment cycles through the possible Gray Code states. Once a data segment, and therefore each data segment because of the concurrency, cycles through the possible Gray code states, the memory device is completely tested. A memory device may, in particular, be a content addressable memory (CAM). A method for testing a priority encoder of a CAM using a Gray Code is also described. Each memory storage location is loaded with a predetermined Gray code representing the address of the memory storage location, each memory storage location differs from an adjacent memory storage location by one data bit.

Abstract: An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.

Abstract: An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.

Abstract: A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the event of a non-match, the new data can be written to the invalid locations in a single clock cycle.

Abstract: An apparatus and method is disclosed for detecting CAM words having a “near match” condition, where “near match” is defined by a CAM word having one or more mismatching bits. Each cell in a CAM word is connected to a match line, where a small known current is impressed upon the line each time a bit does not match with search data. The total current is sensed to establish a priority for each respective CAM word. Each priority for each CAM word is then decoded to determine the Cam word having the highest priority. Under an alternate embodiment, a minimum priority level select circuit is disclosed, where a user may specify an acceptable priority level that is generated from a CAM word search.

Abstract: A signal presence detection device has a first reference voltage generation device in the form of a first voltage divider, a second reference voltage generation device in the form of a second voltage divider and a third reference voltage generation device in the form of a third voltage divider. The detection device also has a signal conditioning device such as a hysteretic amplifier with an output that is coupled to the first and second voltage dividers. A comparison device is coupled to all three voltage dividers to compare a voltage of the first voltage divider to a voltage of the third voltage divider and to compare a voltage of the second voltage divider to the voltage of the third voltage divider. The comparison device is coupled at two outputs thereof to two respective inputs of an XOR device. The XOR device receives respective signals from the first and second outputs of the comparison device and produces a signal presence output that serves to indicate whether an incoming signal is present or absent.

Abstract: A data communication device adapted to receive a data stream includes positive feedback. The positive feedback allows the data communication device to operate with a bi-stable operating characteristic. Consequently the data communication device exhibits superior rejection of signal input noise and reduced chatter. According to various embodiments, the data communication device includes a plurality of component devices having dc coupling therebetween.

Abstract: An apparatus and method for a CAM priority match detection circuit that identifies one or more CAM words from a group of CAM words having a “longest match” that matches the bits in a corresponding comparand register. A decoder uses n input lines and m complement lines to generate 2.sup.n outputs, wherein only one of the outputs will be active. A priority setting circuit resolves an initial matching operation to supply priority values to CAM words, and a priority resolving circuit processes the priority values to determine an overall priority for a group of CAM words.

Abstract: A method and apparatus is presented for providing improved responsiveness of a receiver device. One embodiment includes a receiver device including an avalanche photodiode (APD), a transimpedance amplifier (TIA), and an automatic gain control (AGC) device configured to adjust the reverse bias voltage applied to the APD according to an approximate DC average of the incoming optical signal. A switch in the AGC device may be used to increase or decrease the time constant of an RC combination determining the DC averaging time period, thereby tailoring the response of the AGC device to characteristics of the incoming data pattern. The resulting receiver exhibits improved responsiveness and sensitivity by adapting to varying data patterns including those with data bursts interspersed with gaps.

Abstract: A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.

Abstract: A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.

Abstract: A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if there are multiple matching entries, in some instances only one matching entry has its counter incremented. The counter value can be written or read as part of either the least significant or most significant bits of the CAM entry.

Abstract: A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the event of a non-match, the new data can be written to the invalid locations in a single clock cycle.

Abstract: A content addressable memory (CAM) device is described including a plurality of storage locations, each arranged as a recirculating shift register, and plurality of bit comparators each coupled to a predetermined stage of a respective recirculating shift register for comparing the data contents of the predetermined stage with the data contents of a predetermined stage of a comparand register. The CAM is further coupled to a priority encoder for determining the highest priority match address.

Abstract: A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.