METHOD AND APPARATUS FOR CONTROL OF ANOTHER DEVICE THROUGH AN IDE BUS

Abstract

A method and apparatus for an IDE device to control a second device through an IDE bus. The IDE device includes firmware, a microprocessor, and a plurality of registers. The IDE device can read specific registers in the second device by storing a value indicating the request in a register of the IDE device and issuing an Interrupt signal (INTRQ). An implementation circuit in the second device then makes the contents of the specific register available to be read by the IDE device and clears the INTRQ. Similarly, the IDE device can write to a specific register of the second device by storing the request and the data to be written into predetermined registers in the IDE device and issuing an INTRQ signal. The implementation circuit then causes the data to be written into the specific register of the second device indicated by the request and clears the INTRQ.

Description

BACKGROUND OF INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to control of another device through an Integrated Drive Electronics (IDE) bus. More specifically, an apparatus and method for an IDE device to control another device through the bus, reducing the cost and complexity of a second device communicating with the IDE device, is disclosed.

[0003] 2. Description of the Prior Art

[0004] The modularization of components for many of todays electronic devices has benefited manufacturers and consumers alike. The consumer has the flexibility to select from a variety of components or add additional hardware according to his or her needs. The manufacturer has the advantages of specialization, reducing costs and increasing performance of the particular component. One quite common example of such an arrangement is the ability of the user to add a device, such as an optical disc drive, to a preexisting host computer system.

[0005] As with non-modularized systems, a basic requirement for the proper functionality of the system is establishing a protocol for effective communications between the various components and the host system. Therefore, a variety of industry standard communication protocols have been developed and are currently in use, such as versions of a Universal Serial Bus (USB), Integrated Drive Electronics (IDE), and Small Computer System Interface (SCSI) interfaces as a few examples. As long as the host system and the component utilize the same protocol, communications allowing the proper functioning of the component are possible.

[0006] An obvious communication problem occurs when a user wishes to attach a device that uses one protocol to a system connection using a different protocol, for example connecting an external IDE device to a USB port of the system. In this situation an intermediate device, or bridge, is often used between the device and the host system to permit effective communications.

[0007] FIG. 1 is a functional block diagram of conventional Host-Bridge-Device system 10. The system 10 comprises a host 15, a bridge 20, and a device 25. A first bus interface 30 connects the host 15 with the bridge 20 and allows communications between the host 15 and the bridge 20 according to a first communications protocol. A second bus interface 35 connects the bridge 20 with the device 25 and allows communications between the bridge 20 and the device 25 according to a second communications protocol. The second communications protocol used in the Host-Bridge-Device system 10 is a version of Integrated Device Electronics (IDE).

[0008] The bridge 20 comprises a circuitry 50 to control the operations of bridge 20. The circuitry 50 comprises a microprocessor 60, a memory 65, and a microprocessor interface 55. The bridge 20 further comprises a plurality of registers 75 used for controlling the functions of the bridge 20. The registers 75 may be comprised within the memory 65 or they may be comprised elsewhere within the bridge 20 according to design considerations. The device comprises a microprocessor 90, firmware 95, and a corresponding plurality of registers 85 used for the transfer of data and control instructions to and from the bridge 20. The memory 65 may be volatile and/or non-volatile and is used to store computer code 70 that is executed by the microprocessor 60 to effect control of the bridge 20. The bridge 20 accesses the device 25 through the IDE bus 35 by the reading and writing of data and control instructions to and from the registers 85 in the device 25. The microprocessor 60 controls the bridge 20 to access the device 25 by the reading and writing of data and control instructions to and from the registers 75 in the bridge 20.

[0009] While the above-described circuitry 50 is capable of controlling the operations of bridge 20, the inclusion of the circuitry 50 to control the operations of bridge 20 raises the cost and complexity of the bridge 20.

SUMMARY OF INVENTION

[0010] It is therefore a primary objective of the claimed invention to reduce the cost and complexity of a Host-Bridge-Data Storage Device system by using the data storage device to control the bridge, through an Integrated Device Electronics (IDE) bus.

[0011] Briefly summarized, the preferred embodiment of the claimed invention discloses an apparatus and method that allow the data storage device to control the other device, such as a bridge, through the IDE bus. Because an IDE data storage device already includes the circuitry necessary for control of the other device, the necessary circuitry can be eliminated from the other device. Only a change to the firmware already included in the IDE data storage device is necessary to successfully implement control of the other device through the IDE bus.

[0012] The claimed invention includes an IDE data storage device that can control another device through an IDE bus. A first end of the IDE bus can be connected to the IDE data storage device and a second end of the IDE bus can be connected to a second device, such as a bridge, host computer, or other apparatus, the IDE bus allowing the IDE data storage device and the second device to communicate according to the IDE protocol. The IDE data storage device includes firmware including computer code for implementing control of the second device, a microprocessor for executing the computer code, and a plurality of registers for the transfer of data and control instructions. The second device comprises a plurality of registers and an implementation circuit for carrying out requests received from the IDE data storage device. The implementation circuit preferably is hardwired but may be put into practice using other methods known in the art, such as via firmware or software.

[0013] According to the present invention, the IDE data storage device can read specific registers in the second device by storing a value the request in a predetermined register or registers of the IDE data storage device and issuing an Interrupt signal (INTRQ). The implementation circuit of the second device then makes the contents of the specific register available to be read by the IDE data storage device and clears the INTRQ. Similarly, the IDE data storage device can write to a specific register of the second device by storing the request and the data to be written into a predetermined register or registers in the IDE data storage device and issuing an INTRQ signal. Upon receiving the INTRQ signal, the implementation circuit of the second device then causes the data to be written into the specific register of the second device indicated by the request and clears the INTRQ.

[0014] It is an advantage of the claimed invention that the IDE data storage device can control the second device through an IDE bus, reducing the cost and complexity of the second device when communicating with the IDE data storage device using an IDE communications protocol.

[0015] These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a functional block diagram of conventional Host-Bridge-Device system.

[0017] FIG. 2 is a functional block diagram of Host-Bridge-Device system according to the present invention.

[0018] FIG. 3 is a flowchart of the device according to the present invention reading a bridge register.

[0019] FIG. 4 is a flowchart of the device according to the present invention writing to a bridge register.

DETAILED DESCRIPTION

[0020] In this application, the term Integrated Device Electronics (IDE) is defined to encompass all protocols based upon IDE technology, including Advanced Technology Attachment (ATA), Advanced Technology Attachment Packet Interface (ATAPI), and Serial ATA. In addition, in this application, the term IDE data storage device, such as various forms of data storage devices including a hard disk drive and an optical disc drive, refers to an apparatus requiring an IDE communications connection with a second device for proper functionality.

[0021] FIG. 2 is a functional block diagram of a Host-Bridge-Device system 100 according to the present invention. Where the components and functionality of the components are the same as depicted in FIG. 1, the original reference numbers have been maintained for clarity.

[0022] The system 100 comprises a host computer system 15, a bridge 120, and a data storage device 125. A first bus interface 30 connects the host 15 with the bridge 120 and allows communications between the host 15 and the bridge 120 according to a first communications protocol. A second bus interface 35 connects the bridge 120 with the data storage device 125 and allows communications between the bridge 120 and the data storage device 125 according to a version of Integrated Device Electronics (IDE) communications protocol.

[0023] The data storage device 125 comprises a microprocessor 90, firmware 195 comprising computer code for operating the data storage device 125 and for controlling the bridge 120, and a plurality of registers 85 used for the transfer of data and control instructions to and from the bridge 120. The bridge 120 of the present invention does not comprise the prior art control circuitry 50 depicted in FIG. 1. However, the bridge 120 does comprise a corresponding plurality of registers 75 for realizing the bridge functions. The bridge 120 further comprises an implementation circuit 80 for carrying out requests received from the data storage device 125. The implementation circuit 80 is hardwired in a preferred embodiment of the present invention but another embodiment may employ an implementation circuit that is not hardwired, such as being software instructions coded in firmware or another form of memory.

[0024] As is known in the art, control of the bridge 120 is affected by the reading and writing to and from the registers 75. The present invention utilizes the IDE bus 35 and a firmware-only modified IDE data storage device 25 instead of all those elements inside the dash-lined block 50 in FIG. 1. Please refer to FIG. 3 and FIG. 4 which are flowcharts demonstrating how this is done according to the present invention.

[0025] FIG. 3 illustrates the present invention method of how the IDE data storage device 125 can read one of the registers 75 in the bridge 120. The steps shown in FIG. 3 include the following:

[0026] Step 400: The IDE data storage device 125 stores a first instruction into a first predetermined register 85 in the IDE device 125, the value of the first instruction indicating a read request and which register 75 in the bridge 120 is to be read.

[0027] Step 410: The IDE data storage device 125 sets an Interrupt Request (INTRQ) signal high.

[0028] Step 420: The bridge 120 receives the INTRQ from the IDE data storage device 125 and checks the contents of the first predetermined register 85.

[0029] Step 430: The implementation circuit 80 receives the contents of the first predetermined register 85 and causes the contents of the indicated register 75 to be placed into a second predetermined register 85 in the IDE data storage device 125.

[0030] Step 440: The bridge 120 clears the INTRQ.

[0031] Step 450: The IDE data storage device 125 reads the second predetermined register 85 in the IDE data storage device 125.

[0032] FIG. 4 illustrates the present invention method of how the IDE data storage device 125 can write to one of the registers 75 in the bridge 120. The steps shown in FIG. 4 include the following. Obviously, the order of steps 500 and 510 can be reversed.

[0033] Step 500: The IDE data storage device 125 stores a second instruction into a third predetermined register 85 in the IDE data storage device 125, the value of the second instruction indicating a write request and which register 75 in the bridge 120 to which data is to be written.

[0034] Step 510: The IDE data storage device 125 stores the data that is to be written into the indicated register 75 in the bridge into a fourth predetermined register 85 of the IDE data storage device 125.

[0035] Step 520: The IDE data storage device 125 sets an Interrupt Request (INTRQ) signal high.

[0036] Step 530: The bridge 120 receives the INTRQ from the IDE data storage device 125 and checks the contents of the third predetermined register 85.

[0037] Step 540: The implementation circuit 80 reads the contents of the predetermined register 85 and places the read contents into the register 75 of the bridge 120 indicated by the third predetermined register 85.

[0038] Step 550: The bridge 120 clears the INTRQ.

[0039] It should be obvious that no change in the hardware of the IDE data storage device 125 is required to implement the present invention; only a change in the firmware already existing in a conventional IDE data storage device is needed.

[0040] It should also be obvious that a second device of the present invention (e.g. a bridge, a host computer, or other apparatus) requires compatible implementation circuitry to correctly respond to the control instructions issued by the IDE data storage device. The compatible implementation circuitry preferably is hardwired but may be possible to implement in some other fashion, such as via computer code located in firmware or some other form of memory in the second device. The use of computer code to respond as if it was the preferred compatible implementation circuitry would require the use of a microprocessor to execute the software, increasing the cost of the second device.

[0041] Additionally, the present invention should not be limited to the use of a bridge. For example, there is no reason that the IDE device of the present inverition could not be directly connected to a host computer (or other apparatus) that comprises either a software form or a hardwired form of the implementation circuitry. All that is required for the IDE data storage device of the present invention to control a second device through an IDE bus connecting the IDE data storage device with the second device is that the second device be compatible. A compatible device is defined as comprising the compatible implementation circuitry so that the compatible device responds to instructions issued by the IDE data storage device as described above.

[0042] It is an advantage of the claimed invention that the IDE data storage device can control a second device through an IDE bus, reducing hardware requirements, cost, and complexity of the second device.

[0043] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A data storage device comprising:

a microprocessor for execution of computer code;

a memory comprising the computer code to be executed, the computer code capable of controlling a compatible device through an Integrated Device Electronics (IDE) bus, the IDE bus connecting the data storage device with the compatible device; and

a plurality of registers utilized by the computer code to control the compatible device.

2. The data storage device of claim 1 wherein the compatible device is a bridge, the bridge connected to a host computer system.

3. The data storage device of claim 2 wherein the bridge communicates with the host computer system utilizing a communication protocol incompatible with an IDE communications protocol.

4. The data storage device of claim 1 wherein the compatible device comprises a plurality of registers and an implementation circuit, the implementation circuit capable of decoding and acting on a first or second instruction issued by the data storage device when the compatible device receives an Interrupt Request (INTRQ) issued by the data storage device.

5. The data storage device of claim 4 wherein the implementation circuit is hardwired.

6. The data storage device of claim 4 wherein the implementation circuit is encoded in software or firmware.

7. The data storage device of claim 4 wherein when the first instruction is decoded by the implementation circuit, the implementation circuit causes a value in a register of the compatible device indicated by a value in a first predetermined register of the data storage device to be transmitted to the data storage device and clears the INTRQ signal.

8. The data storage device of claim 4 wherein when the second instruction is decoded by the implementation circuit, the implementation circuit causes a value in a fourth predetermined register of the data storage device to be stored into a register of the compatible device indicated by a value in a third predetermined register of the data storage device and clears the INTRQ signal.

9. A method for a data storage device to control a compatible device through a connecting Integrated Device Electronics (IDE) bus, the data storage device comprising a microprocessor for execution of computer code, a plurality of registers, and a memory comprising computer code capable of controlling the compatible device, the

compatible device comprising an implementation circuit and a plurality of registers, the method comprising:

the computer code causing a first or second instruction to be stored in a first predetermined register of the data storage device;

the computer code causing an Interrupt Request (INTRQ) signal to be transmitted from the data storage device to the compatible device;

the compatible device receiving the INTRQ;

the implementation circuit decoding and acting on the control instruction; and

the compatible device clearing the INTRQ signal.

10. The method of claim 9 wherein when the implementation circuit decodes the first instruction, acting on the first instruction comprises:

the implementation circuit causing a value in a register of the compatible device indicated by a value in a first predetermined register of the data storage device to be transmitted to the data storage device and clearing the INTRQ signal.

11. The method of claim 9 wherein when the implementation circuit decodes the second instruction, acting on the second instruction comprises:

the implementation circuit causing a value in a fourth predetermined register of the data storage device to be stored into a register of the compatible device indicated by a value in a third predetermined register of the data storage device and clearing the INTRQ signal.

12. The method of claim 9 wherein the compatible device is a bridge, the bridge connected to a host computer system.

13. The method of claim 9 wherein the implementation circuit is hardwired.

14. The method of claim 9 wherein the implementation circuit is encoded in software or firmware.

15. A bridge for use in a Host-Bridge-Device system, the bridge connected to the device by an Integrated Device Electronics (IDE) bus, the device comprising a plurality of registers, a microprocessor, and memory comprising computer code capable of issuing a first or second instruction to the bridge, the bridge comprising:

a plurality of resisters; and

an implementation circuit capable of decoding and acting upon the first or second instruction issued by the device when the bridge receives an Interrupt Request (INTRQ) issued by the device.

16. The bridge of claim 15 wherein when the implementation circuit decodes the first instruction, acting on the first instruction comprises the implementation circuit causing a value in a register of the bridge indicated by a value in a first predetermined register of the device to be transmitted to the device and clearing the INTRQ signal.

17. The bridge of claim 15 wherein when the implementation circuit decodes the second instruction, acting on the second instruction comprises the implementation circuit causing a value in a fourth predetermined register of the device to be stored into a register of the bridge indicated by a value in a third predetermined register of the device and clearing the INTRQ signal.

18. The bridge of claim 15 wherein the device is a hard disk drive or an optical disc drive.

19. The bridge of claim 15 wherein the implementation circuit in hardwired.

20. A device that controls the bridge of claim 15 by issuing the first or second instruction to the bridge.