Alpha particle shields in chip packaging
A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.
1. Technical Field
The present invention relates to integrated circuit packaging, and more specifically, to using alpha particle shields in integrated circuit packaging.
2. Related Art
In flip-chip technologies, solder bumps are typically formed on top of a semiconductor chip (i.e., integrated circuit IC). Each solder bump is formed directly on a bond pad of the chip. Then the chip is flipped face down and then aligned to a package/substrate so that the solder bumps are bonded directly, simultaneously, and one-to-one to the pads of the package/substrate (called package/substrate pads). However, for ceramic substrates, alpha particles (large subatomic fragments consisting of 2 protons and 2 neutrons) continuously emit from the substrate and enter the chip resulting in a large number of soft errors in the chip during the normal operation of the chip. Alpha particles are also generated from 210Pb contained in the solder bumps.
Therefore, there is a need for a structure (and a method for forming the same) that reduces the number of alpha particles that enter the chip.
SUMMARY OF THE INVENTIONThe present invention provides a structure, comprising (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; (b) N solder bumps corresponding to the N chip electric pads; (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps; and (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.
The present invention also provides a structure, comprising (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; (b) N solder bumps corresponding to the N chip electric pads; (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps, wherein the semiconductor interposing shield has a thickness of at least 50 μm; (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads; and (e) a ceramic substrate including N substrate pads, wherein the N solder bumps are bonded to the N substrate pads.
The present invention also provides a structure fabrication method, comprising providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; providing an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side; bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors; polishing the bottom side of the interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield after said bonding the integrated circuit to the top side is performed; and forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.
The present invention also provides a structure fabrication method, comprising providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; providing a semiconductor interposing shield having a top side and a bottom side and having N electric conductors in the semiconductor shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side; bonding the integrated circuit to the top side of the semiconductor interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors; polishing the bottom side of the semiconductor interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the semiconductor interposing shield after said bonding the integrated circuit to the top side is performed; forming N solder bumps on the polished bottom side of the semiconductor interposing shield and in electrical contact with the N electric conductors; after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps, wherein the semiconductor interposing shield comprises essentially only silicon, and wherein the semiconductor interposing shield has a thickness of at least 50 μm after said polishing the bottom side is performed.
The present invention provides a structure (and a method for forming the same) that reduces the number of alpha particles that enter the chip.
BRIEF DESCRIPTION OF THE DRAWINGS
Next, with reference to
Next, with reference to
Next, in one embodiment, a chemical mechanical polishing (CMP) step is performed on top surfaces 320 of the interposing shield 100 of
Next, with reference to
Next, with reference to
Next, in one embodiment, the oxide layer 420 is recessed so that its top surface 422 is lower than the top surfaces 512 of the electric pads 510a and 510b as shown in
Next, with reference to
Next, with reference to
Next, with reference to
Next, with reference to
Next, with reference to
Next, in one embodiment, the structure 700 is placed in a package (not shown) having package pins (not shown) that are electrically connected to the substrate pads 1010a and 1010b via metal lines (not shown).
In summary, with reference to
In one embodiment, the thickness 114 of the interposing shield 100 is sufficiently large such that at least a pre-specified percentage of alpha particles entering the interposing shield 100 from the ceramic substrate 1010 do not pass through the interposing shield 100 so as to reach the semiconductor chip 600.
It should be noted that the thickness 114 of the interposing shield 100 is essentially the depth 113 (
It should also be noted that the annular electric conductors 410a and 410b provide electric paths from the solder bumps 910a and 910b to the devices (not shown) of the semiconductor chip 600 (via the electric pads 510a,622a and electric pad 510b,622b, respectively). The annular shape is chosen for the electric conductors 410a and 410b so as to save metal material during the step of filling the trenches 112a and 112b (
It should be noted that the solder bumps 910a and 910b may comprise a tin-lead alloy which itself generates alpha particles. Because the interposing shield 100 is sandwiched between the solder bumps 910a and 910b and the semiconductor chip 600, the interposing shield 100 also helps reduce the alpha particles that enter the semiconductor chip 600 from the solder bumps 910a and 910b.
In one embodiment, the structure 700 comprises a dielectric layer (not shown) that electrically insulates the electric chip pads 920a and 920b from the silicon region of the silicon layer 110 such that there is no electrically conducting path between the electric chip pads 920a and 920b through the silicon region of the silicon layer 110.
In the embodiments above, there are two trenches 112a and 112b (
In one embodiment, with reference to
In one embodiment, a metal (e.g., copper) layer 1210 (
In one embodiment, the silicon regions of the semiconductor interposing shield 100 are doped with boron atoms (using, illustratively, ion implantation). This enhances the capability of the semiconductor interposing shield 100 in preventing cosmic thermal neutrons from passing through the semiconductor interposing shield 100 and reach the semiconductor chip 600. The cosmic thermal neutrons undergo reactions with the B that emit <2 MeV alpha particles. Therefore it is advantageous to have this B doped region on the top of the Si interposer layer (on the opposite side from the semiconductor device).
While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims
1. A structure, comprising:
- (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;
- (b) N solder bumps corresponding to the N chip electric pads;
- (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps; and
- (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.
2. The structure of claim 1, wherein the semiconductor interposing shield has a thickness of at least 50 μm.
3. The structure of claim 1, wherein the semiconductor interposing shield has a thickness sufficiently large such that at least a pre-specified percentage of alpha particles entering the semiconductor interposing shield do not pass through the semiconductor interposing shield.
4. The structure of claim 3, wherein the semiconductor interposing shield comprises metal regions embedded in the semiconductor interposing shield, wherein the metal regions are electrically insulated from the N electric conductors.
5. The structure of claim 1, wherein the N electric conductors are electrically insulated from the semiconductor interposing shield.
6. The structure of claim 1, wherein each conductor of the N electric conductors has an annular shape.
7. The structure of claim 1, further comprising a ceramic substrate including N substrate pads, wherein the N solder bumps are bonded to the N substrate pads.
8. A structure, comprising:
- (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;
- (b) N solder bumps corresponding to the N chip electric pads;
- (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps, wherein the semiconductor interposing shield has a thickness of at least 50 μm;
- (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads; and
- (e) a ceramic substrate including N substrate pads, wherein the N solder bumps are bonded to the N substrate pads.
9. The structure of claim 8, wherein the semiconductor interposing shield has a thickness sufficiently large such that at least a pre-specified percentage of alpha particles entering the semiconductor interposing shield from the ceramic substrate do not pass through the semiconductor interposing shield to reach the integrated circuit.
10. The structure of claim 8, wherein the semiconductor interposing shield comprises boron dopants.
11. The structure of claim 8, further comprising a metal layer sandwiched between and electrically insulated from the semiconductor interposing shield and the N solder bumps.
12. The structure of claim 11, wherein the metal layer has a thickness of less than 15 cm, and wherein the semiconductor interposing shield has a thickness in a range of 30 μm-70 μm.
13. The structure of claim 11, wherein the metal layer has a thickness in a range of 10 μm-15 μm, and wherein the semiconductor interposing shield has a thickness of less than 1 μm.
14. A structure fabrication method, comprising:
- providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;
- providing an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side;
- bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors;
- polishing the bottom side of the interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield after said bonding the integrated circuit to the top side is performed; and
- forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.
15. The method of claim 14, further comprising, after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps.
16. The structure of claim 14, wherein the interposing shield comprises essentially only a semiconductor material.
17. The structure of claim 16, wherein the interposing shield has a thickness of at least 50 μm after said polishing the bottom side is performed.
18. The method of claim 14, wherein said providing the interposing shield comprises:
- providing a semiconductor layer;
- creating N trenches in the semiconductor layer;
- filling the N trenches with an electrically conducting material so as to form the N electric conductors, wherein the semiconductor layer, after said filling the N trenches is performed, comprises the interposing shield.
19. The method of claim 18, wherein said providing the interposing shield further comprises forming a dielectric layer on side walls of the N trenches before said filling the N trenches is performed.
20. The method of claim 18, wherein each trench of the N trenches has an annular shape.
21. A structure fabrication method, comprising:
- providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;
- providing a semiconductor interposing shield having a top side and a bottom side and having N electric conductors in the semiconductor shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side;
- bonding the integrated circuit to the top side of the semiconductor interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors;
- polishing the bottom side of the semiconductor interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the semiconductor interposing shield after said bonding the integrated circuit to the top side is performed;
- forming N solder bumps on the polished bottom side of the semiconductor interposing shield and in electrical contact with the N electric conductors; and
- after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps,
- wherein the semiconductor interposing shield comprises essentially only silicon, and
- wherein the semiconductor interposing shield has a thickness of at least 50 μm after said polishing the bottom side is performed.
22. The method of claim 21, wherein said providing the semiconductor interposing shield comprises:
- providing a semiconductor layer;
- creating N trenches in the semiconductor layer;
- filling the N trenches with an electrically conducting material so as to form the N electric conductors, wherein the semiconductor layer, after said filling the N trenches is performed, comprises the semiconductor interposing shield.
Type: Application
Filed: Aug 24, 2005
Publication Date: Mar 1, 2007
Inventors: Paul Andry (Yorktown Heights, NY), Cyril Cabral (Mahopac, NY), Kenneth Rodbell (Sandy Hook, CT), Robert Wisnieff (Ridgefield, CT)
Application Number: 11/211,116
International Classification: H01L 23/48 (20060101);