Patents by Inventor Kenneth Rodbell
Kenneth Rodbell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10957659Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: GrantFiled: May 23, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenneth Rodbell, Davood Shahrjerdi
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Patent number: 10566297Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: GrantFiled: October 5, 2017Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenneth Rodbell, Davood Shahrjerdi
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Publication number: 20190279946Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Inventors: Kenneth Rodbell, Davood Shahrjerdi
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Patent number: 9997475Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: GrantFiled: January 13, 2016Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenneth Rodbell, Davood Shahrjerdi
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Publication number: 20180033906Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: ApplicationFiled: October 5, 2017Publication date: February 1, 2018Inventors: Kenneth Rodbell, Davood Shahrjerdi
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Publication number: 20170200684Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: Kenneth Rodbell, Davood Shahrjerdi
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Patent number: 8080805Abstract: A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.Type: GrantFiled: March 9, 2010Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Michael Gordon, Steven Koester, Kenneth Rodbell, Jeng-Bang Yau
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Publication number: 20110220805Abstract: A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.Type: ApplicationFiled: March 9, 2010Publication date: September 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Gordon, Steven Koester, Kenneth Rodbell, Jeng-Bang Yau
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Publication number: 20070247896Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.Type: ApplicationFiled: April 24, 2006Publication date: October 25, 2007Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen Kosonocky, Sampath Purushothaman, Kenneth Rodbell
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Patent number: 7186166Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.Type: GrantFiled: November 14, 2005Date of Patent: March 6, 2007Assignees: International Business Machines Corporation, Freudenberg Nonwovens Ltd.Inventors: Shyng-Tsong Chen, Kenneth Davis, Oscar Kai Chi Hsu, Kenneth Rodbell, Jean Vangsness
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Publication number: 20070045844Abstract: A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.Type: ApplicationFiled: August 24, 2005Publication date: March 1, 2007Inventors: Paul Andry, Cyril Cabral, Kenneth Rodbell, Robert Wisnieff
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Publication number: 20070042586Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.Type: ApplicationFiled: October 20, 2006Publication date: February 22, 2007Applicant: International Business Machines CorporationInventors: Roy Carruthers, Cedrik Coia, Christophe Detavernier, Christian Lavoie, Kenneth Rodbell
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Publication number: 20070013073Abstract: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.Type: ApplicationFiled: July 18, 2005Publication date: January 18, 2007Inventors: Cyril Cabral, Michael Gordon, Kenneth Rodbell
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Publication number: 20060116059Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.Type: ApplicationFiled: November 14, 2005Publication date: June 1, 2006Applicants: International Business Machines Corporation, Freudenberg Nonwovens Ltd.Inventors: Shyng-Tsong Chen, Kenneth Davis, Oscar Hsu, Kenneth Rodbell, Jean Vangsness
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Publication number: 20060071338Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Petrarca, Mahadevaiyer Krishnan, Michael Lofaro, Kenneth Rodbell
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Publication number: 20060017169Abstract: A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.Type: ApplicationFiled: June 29, 2005Publication date: January 26, 2006Applicant: International Business Machines CorporationInventors: Panayotis Andricacos, Hariklia Deligianni, John Dukovic, Daniel Edelstein, Wilma Horkans, Chao-Kun Hu, Jeffrey Hurd, Kenneth Rodbell, Cyprian Uzoh, Kwong-Hon Wong
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Patent number: 6964604Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.Type: GrantFiled: April 5, 2004Date of Patent: November 15, 2005Assignees: International Business Machines Corporation, Freudenberg Nonwovens Ltd.Inventors: Shyng-Tsong Chen, Kenneth Davis, Oscar Kai Chi Hsu, Kenneth Rodbell, Jean Vangsness
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Publication number: 20050250319Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.Type: ApplicationFiled: May 4, 2004Publication date: November 10, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roy Carruthers, Cedrik Coia, Christophe Detavernier, Christian Lavoie, Kenneth Rodbell
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Publication number: 20050199502Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.Type: ApplicationFiled: May 6, 2005Publication date: September 15, 2005Applicant: International Business Machines CorporationInventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Horkans, Keith Kwietniak, Michael Lane, Sandra Malhotra, Fenton McFeely, Conal Murray, Kenneth Rodbell, Philippe Vereecken
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Publication number: 20050143945Abstract: Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.Type: ApplicationFiled: December 12, 2003Publication date: June 30, 2005Applicant: IBM CorporationInventors: Carl Bohnenkamp, Ethan Cannon, Ethan Cascio, Michael Gordon, Kenneth Rodbell, Theodore Zabel