Floorplanning A Hierarchical Physical Design To Improve Placement And Routing
Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.
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This patent application claims the benefit of copending U.S. Provisional Patent Application, Ser. No. 60/465115, filed Apr. 23, 2003, entitled “ADVANCED BLOCK FLOORPLANNING IN ABUTTED HIERARCHICAL CHIP DESIGN,” by Paul Rodman.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to floorplanning a physical design for an integrated circuit chip. More particularly, the present invention relates to the field of floorplanning a hierarchical physical design to improve placement and routing.
2. Related Art
The process of generating a physical design for an integrated circuit chip is complicated. The physical design represents the layout of the integrated circuit chip on a semiconductor, such as silicon, and is utilized to fabricate the integrated circuit chip. There are several types of physical designs: flat physical designs and hierarchical physical designs. Typically, the physical design is generated in several stages. Examples of these stages include floorplanning, placement, routing, and verification. In a flat physical design these stages are sequentially performed on the entire layout, while in a hierarchical physical design these stages are sequentially performed on partitions of the layout referred as blocks (or place-and-route blocks).
Floorplanning is performed before placement and routing. Thus, floorplanning affects subsequent stages such as placement and routing. The main goal and objective of floorplanning is creating a floorplan. The floorplan can determine whether placement and routing are possible for the physical design.
During the top-level floorplanning stage of a hierarchical physical design, blocks are arranged on a selected chip area and chip shape. In arranging the blocks, individual blocks are sized and shaped. These blocks can have any number of cells that execute digital or analog functions (e.g., NAND, NOR, D flip-flop, etc.) by connectively grouping circuit elements such as transistors, capacitors, resistors, and other circuit elements. Moreover, these blocks can have one or more macrocells. A macrocell is a functional module such as RAM, ROM, ALU, etc. Each of these cells and macrocells has one or more ports (or terminals) for inputting signals or outputting signals, each of which, in turn, may connect to one or more ports of other cells and macrocells via metal wires. A net is a set of two or more ports that are connected. Generally, the input to the floorplanning stage is a netlist for the integrated circuit chip. A netlist is a list of nets for the integrated circuit chip.
Continuing, the location of Input/Output blocks is determined. These Input/Output blocks facilitate connections/communication with external components. An Input/Output block may have bonding pad cells or bump cells. Moreover, power distribution and clock distribution are determined during the top-level floorplanning stage of the hierarchical physical design. Furthermore, the top-level floorplanning stage is performed with the objectives of minimizing the chip area and minimizing delay.
SUMMARY OF THE INVENTIONMethods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.
In another embodiment, a method of floorplanning a hierarchical physical design includes performing an initial flat placement using a netlist of the hierarchical physical design. Continuing, a plurality of partitions of the netlist in the initial flat placement are identified, wherein each partition has a boundary. Moreover, a top-level floorplan for the hierarchical physical design is generated using the initial flat placement. In generating the top-level floorplan, a corresponding block for each identified partition is generated by converting the boundary of the identified partition into a plurality of edges. The plurality of edges includes at least one stepped-shape edge.
In yet another embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. An area unoccupied by the blocks and surrounding at least one of the blocks is selected. Moreover, the area is designated as an additional block, wherein the additional block has a gap where the surrounded block is located.
In still another embodiment, a method of floorplanning a physical design includes assigning a priority attribute to each one of a plurality of blocks. Each priority attribute determines which block owns any overlap area relative to another block. Continuing, the blocks are arranged to form one or more overlap areas. Each overlap area is allocated to one of the blocks based on the assigned priority attribute of the blocks.
In another embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Moreover, a plurality of nets is routed in the top-level of the hierarchical physical design to determine pin locations for each block. Each pin of each block represents one of a location where a signal enters the block and a location where a signal exits the block. Continuing, it is determined whether a routed net includes a plurality of segments within a block. Furthermore, one or more of the segments are renamed.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the present invention.
Reference will now be made in detail to embodiments of the present invent on, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details.
Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described herein. The following description of the invention is applicable to physical designs for integrated circuit chips. Moreover, the invention can be practiced on the entire physical design. Additionally, the invention can be practiced on a portion of the physical design, and then this portion of the physical design can be integrated with the rest of the physical design.
Although the description of the invention will focus on hierarchical physical designs, it should be understood that the invention is applicable to other types of physical designs. Moreover, the description of the invention will focus on an abutted-pin hierarchical physical design. It should be understood that the invention is applicable to other types of hierarchical physical designs.
A detailed description of an abutted-pin hierarchical physical design can be found in the co-pending, commonly-owned U.S. patent application Ser. No. 09/714,722, filed on Nov. 15, 2000, entitled “OPTIMIZATION OF ABUTTED-PIN HIERARCHICAL PHYSICAL DESIGN”, by Dahl et al., which is incorporated herein by reference.
As discussed above, the floorplanning stage of a hierarchical physical design affects subsequent physical design stages such as placement and routing. If the floorplanning stage takes into account the goals, objectives, and causes of problems associated with the placement and routing stages, a floorplan is generated which can facilitate, enhance, and optimize the placement and routing stages.
Hence, the entire chip area and chip shape utilized in the top-level floorplan 100A is covered with blocks 10-30 and 60-94. Another distinguishing feature of the top-level floorplan 100A of an abutted-pin hierarchical physical design is the merging of traditional top-level components or objects (e.g., timing components, clock distribution wiring, power distribution wiring, repeaters, buffers, etc.) into the individual blocks 10-30 and 60-94 and corresponding block-level netlists.
Continuing with
As described above, blocks 10-30 and 60-94 can have cells and macrocells. Each of these cells and macrocells has one or more ports (or terminals) for inputting signal or outputting signals, each of which, in turn, may connect to one or more ports of other cells and macrocells via metal wires. A net is a set of two or more ports that are connected.
Each block 10-30 and 60-94 has one or more pins 50. Each pin 50 of a block 10-30 and 60-94 represents a location where a signal enters the block or a location where a signal exits the block. The pins 50 are utilized in placing and routing each block during block-level operations. At the top-level of a hierarchical physical design (e.g., an abutted-pin hierarchical physical design), a router is used to route nets representing two or more ports of different blocks that are connected. In general, a location of a pin 50 is defined where the routing wire crosses the boundary or edge 40 of the block. Since boundaries or edges 40 of one block 10-30 and 60-94 abut boundaries or edges 40 of another block 10-30 and 60-94, the pin 50 of one block 10-30 and 60-94 abuts the pin 50 of another block 10-30 and 60-94, as shown in the top-level floorplan 100A for an abutted-pin hierarchical physical design in
After analyzing the first top-level floorplan 200, it is determined that the size of at least one of the blocks 210, 220, and 230 has to be increased in order to successfully complete the placement and routing phases at the block-level. However, there is no additional space in the core area. In one solution, a larger chip area and/or different chip shape is selected. This solution significantly increases costs. In a second solution, the size of at least one of the blocks 210, 220, and 230 is decreased sufficiently to meet the demand for additional space in the core area, but the decrease in size does not cross the threshold that prevents successfully completion of the placement and routing phases at the block-level. In general, this results in a floorplan having one or more rectilinear blocks.
A second top-level floorplan 300A of the core area of a hierarchical physical design in accordance with an embodiment of the present invention is shown in
A third top-level floorplan 300B of the core area of a hierarchical physical design in accordance with an embodiment of the present invention is shown in
Both the second top-level floorplan 300A and the third top-level floorplan 300B are not efficient and optimal because the rectilinear shapes of blocks 210, 220, and 230 (
A method of floorplanning a hierarchical physical design is depicted in
Referring to
A method of floorplanning a hierarchical physical design is depicted in
In particular, the initial flat placement 500A will be used to generate a top-level floorplan.
A method of floorplanning a hierarchical physical design is depicted in
Further,
The block 610 having gaps of
Moreover, the block 610 having gaps of
A method of floorplanning a physical design is show in
Referring to
A method of floorplanning a hierarchical physical design is shown in
In an embodiment, the methods of the present invention are performed by computer-executable instructions stored in a computer-readable medium, such as a magnetic disk, CD-ROM, an optical medium, a floppy disk, a flexible disk, a hard disk, a magnetic tape, a RAM, a ROM, a PROM, an EPROM, a flash-EPROM, or any other medium from which a computer can read.
With reference to
Computer system 900 includes an address/data bus 110 for communicating information, a central processor 101 coupled with bus 110 for processing information and instructions, a volatile memory 102 (e.g., random access memory RAM) coupled with the bus 110 for storing information and instructions for the central processor 101 and a non-volatile memory 103 (e.g., read only memory ROM) coupled with the bus 110 for storing static information and instructions for the processor 101. Exemplary computer system 900 also includes a data storage device 104 “disk subsystem”)such as a magnetic or optical disk and disk drive coupled with the bus 110 for storing information and instructions. Data storage device 104 can include one or more removable magnetic or optical storage media (e.g., diskettes, tapes) which are computer-readable memories. Memory units of computer system 900 include volatile memory 102, non-volatile memory 103 and data storage device 104.
Exemplary computer system 900 can further include a signal generating device 108 (e.g., a network interface card “NIC”) coupled to the bus 110 for interfacing with other computer systems. Also included in exemplary computer system 900 of
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
Claims
1. A method of floorplanning a hierarchical physical design, said method comprising:
- performing an initial flat placement using a netlist of said hierarchical physical design;
- identifying a plurality of partitions of said netlist in said initial flat placement, wherein each partition has a boundary; and
- generating a top-level floorplan for said hierarchical physical design using said initial flat placement, wherein said generating said top-level floorplan includes generating a corresponding block for each identified partition by converting said boundary of said identified partition into a plurality of edges, and wherein said plurality of edges includes at least one stepped-shape edge.
2. The method as recited in claim 1 wherein said generating said top-level floorplan includes:
- using a curve fitting technique to form said stepped-shape edge.
3. The method as recited in claim 1 wherein said hierarchical physical design is an abutted-pin hierarchical physical design.
4. The method as recited in claim 3 wherein said abutted-pin hierarchical physical design includes a top-level and a block-level.
5. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of floorplanning a hierarchical physical design, said method comprising:
- performing an initial flat placement using a netlist of said hierarchical physical design;
- identifying a plurality of said netlist in said initial flat placement, wherein each partition has a boundary; and
- generating a top-level floorplan for said hierarchical physical design using said initial flat placement, wherein said generating said top-level floorplan includes generating a corresponding block for each identified partition by converting said boundary of said identified partition into a plurality of edges, and wherein said plurality of edges includes at least one stepped-shape edge.
6. The computer-readable medium as recited in claim 5 wherein said generating said top-level floorplan includes:
- using a curve fitting technique to form said stepped-shape edge.
7. The computer-readable medium as recited in claim 5 wherein said hierarchical physical design is an abutted-pin hierarchical physical design.
8. The computer-readable medium as recited in claim 7 wherein said abutted-pin hierarchical physical design includes a top-level and a block-level.
Type: Application
Filed: Dec 8, 2006
Publication Date: Jun 14, 2007
Applicant: MAGMA DESIGN AUTOMATION, INC. (Santa Clara, CA)
Inventor: Paul Rodman (Palo Alto, CA)
Application Number: 11/608,689
International Classification: G06F 17/50 (20060101);