CHIP UNDERFILL IN FLIP-CHIP TECHNOLOGIES
A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
1. Technical Field
The present invention relates to flip-chip technologies, and more specifically, to flip chip underfill in flip-chip technologies.
2. Related Art
In flip-chip technologies, chip solder balls are typically formed on top of a semiconductor chip and then the chip is flipped upside down and bonded to a substrate.
The difference in thermal expansion coefficients of the chip and the substrate may cause solder ball fatigue or cracking in the chip resulting in chip failure. Therefore, there is a need for a structure (and a method for forming the same) in which the difference between thermal expansion coefficients of the chip and the substrate does not cause solder ball fatigue or chip cracking as in the prior art.
SUMMARY OF THE INVENTIONThe present invention provides a semiconductor structure, comprising (a) a substrate; (b) a chip which includes N chip solder balls, wherein N is a positive integer, and wherein the N chip solder balls are in electrical contact with the substrate; (c) a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate; and (d) a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes (a) a substrate, (b) a chip which includes N chip solder balls, wherein N is a positive integer, and wherein the N chip solder balls are in electrical contact with the substrate; after said providing is performed, forming a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate; and after said forming the first, second, third, and fourth corner underfill regions is performed, forming a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
The present invention provides a structure (and a method for forming the same) in which the difference between thermal expansion coefficients of the chip and the substrate does not cause solder ball fatigue or chip cracking.
BRIEF DESCRIPTION OF THE DRAWINGS
In one embodiment, the semiconductor structure 100 is formed according to the following fabrication process. Illustratively, the fabrication process starts with the formation of the chip 120. The chip solder balls 140 are then formed on top of the chip 120 wherein the chip solder balls 140 are electrically connected to devices (not shown) in the chip 120 via chip bond pads (not shown). Next, in one embodiment, the chip 120 is flipped upside down and bonded to the laminate substrate 110 such that the chip solder balls 140 of the chip 120 are directly and one-to-one bonded with substrate bond pads (not shown) on the laminate substrate 110. Next, in one embodiment, the four corner underfill regions 160a, 160b, 160c, and 160d are formed by dispensing a corner underfill material to the four corner spaces between the chip 120 and the laminate substrate 110. In one embodiment, the corner underfill material has a coefficient of thermal-expansion (CTE) in a range of 20-30 ppm/° C., has an elastic modulus (E) in a range of 7-10 Gpa, and has a glass transition temperature (Tg) in a range of 90-110° C. Next, in one embodiment, the main underfill region 130 is formed by dispensing a main underfill material to the remaining empty spaces between the chip 120 and the laminate substrate 110. In one embodiment, the main underfill material has a coefficient of thermal-expansion (CTE) of about 25 ppm/° C., has an elastic modulus (E) of about 9.5 Gpa, and has a glass transition temperature (Tg) of about 94° C.
In one embodiment, the laminate substrate 110 comprises substrate solder balls 150 which electrically connect the chip solder balls 140 to a printed wire board (not shown) via the conducting lines (not shown) in the laminate substrate 110. In one embodiment, the laminate substrate 110 comprises E679FG-R, a dielectric material made by Hitachi Semiconductor In one embodiment, the corner underfill material is selected so as to reduce thermo-mechanical strains of the chip solder balls 140 at four corner regions 160a, 160b, 160c, and 160d.
In one embodiment, the shape of the portions of the four corner underfill regions 160a, 160b, 160c, and 160d which are sandwiched between the chip 120 and the substrate 110 are approximately a quarter circle since the corner underfill material is dispensed by capillary action in all directions from the four corners. In one embodiment, the radius of the quarter circle shape is in a range of 0.5 mm-1.0 mm.
In one embodiment, the sizes and shapes of the chip solder balls 140 at the four corner regions of the chip 120 are chosen so as to reinforce the bond between the chip 120 and the laminate substrate 110 by (a) increasing the size of the footprint of the corner solder connection or by (b) placing additional, smaller dummy (non-functional) solder balls 140 at the four corner regions 160a, 160b, 160c, and 160d. More details are below with reference to
In one embodiment, the four corner regions of the chip 120 have a lower chip solder ball concentration than the other regions of the chip 120.
In one embodiment, the four corner regions of the chip 120 have a higher chip solder ball concentration than the other regions of the chip 120.
While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims
1. A semiconductor structure, comprising:
- (a) a substrate;
- (b) a chip which includes N chip solder balls, wherein N is a positive integer, wherein the N chip solder balls comprise a solder material, and wherein the N chip solder balls are in electrical contact with the substrate;
- (c) a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrates, wherein each corner underfill region of the first, second, third, and fourth corner underfill regions is in direct physical contact with at least one chip solder ball of the N chip solder balls; and
- (d) a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
2. The structure of claim 1,
- wherein each corner underfill region of the first, second, third, and fourth corner underfill regions has essentially a quarter circle shape whose radius is in a range of 0.5 mm to 1 mm.
3. The structure of claim 1, wherein each of chip solder balls of the N chip solder balls in the first, second, third, and fourth corner underfill regions has a first size which is different from a second size of chip solder balls of the N chip solder balls in the main underfill region.
4. The structure of claim 3, wherein the first size is greater than the second size.
5. The structure of claim 3, wherein the first size is smaller than the second size.
6. The structure of claim 1, wherein a chip solder ball in the first corner region has an L shape.
7. The structure of claim 1, wherein a first concentration of chip solder balls in four corners of the chip is different from a second concentration of chip solder balls in other regions of the chip.
8. The structure of claim 7, wherein the first concentration is greater than the second concentration.
9. The structure of claim 7, wherein the first concentration is smaller than the second concentration.
10. The structure of claim 1,
- wherein the corner underfill material has a CTE (coefficient of thermal-expansion) in a range of 20-30 ppm/° C., and
- wherein the corner underfill material has a modulus in a range of 7-10 Gpa.
11. The structure of claim 1, wherein the corner underfill material has a glass transition temperature (Tg) in a range of 90-110° C.
12. A semiconductor structure fabrication method, comprising:
- providing a semiconductor structure which includes (a) a substrate, (b) a chip which includes N chip solder balls, wherein N is a positive integer, wherein the N chip solder balls comprise a solder material, and wherein the N chip solder balls are in electrical contact with the substrate;
- after said providing is performed, forming a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate, wherein each corner underfill region of the first, second, third, and fourth corner underfill regions is in direct physical contact with at least one chip solder ball of the N chip solder balls; and
- after said forming the first, second, third, and fourth corner underfill regions is performed, forming a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
13. The method of claim 12,
- wherein each corner underfill region of the first, second, third, and fourth corner underfill regions has essentially a quarter circle shape whose radius is in a range of 0.5 mm to 1 mm.
14. The method of claim 12, wherein each of chip solder balls of the N chip solder balls in the first, second, third, and fourth corner underfill regions has a first size which is different from a second size of chip solder balls of the N chip solder balls in the main underfill region.
15. The method of claim 12, wherein a chip solder ball in the first corner region has an L shape.
16. The method of claim 12, wherein a first concentration of chip solder balls in four corners of the chip is different from a second concentration of chip solder balls in other regions of the chip.
17. The method of claim 16, wherein the first concentration is greater than the second concentration.
18. The method of claim 16, wherein the first concentration is smaller than the second concentration.
19. The method of claim 12, wherein said forming the first, second, third, and fourth corner underfill region comprises dispensing the corner underfill material to the four corners of the chip resulting in the first, second, third, and fourth corner underfill region.
20. The method of claim 19, wherein said forming the main underfill region comprises dispensing the main underfill material to remaining empty spaces between the chip and the substrate resulting in the main underfill region.
Type: Application
Filed: Feb 27, 2006
Publication Date: Aug 30, 2007
Inventors: Timothy Daubenspeck (Colchester, VT), Jeffrey Gambino (Westford, VT), Christopher Muzzy (Burlington, VT), Wolfgang Sauter (Richmond, VT), David Questad (Hopewell Junction, VT)
Application Number: 11/276,380
International Classification: H01L 21/50 (20060101); H01L 23/34 (20060101);