Column sample-and-hold cell for CMOS APS sensor
A sample and hold readout circuit, and method of operation which minimizes fixed pattern noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output. This is accomplished by eliminating the crowbar between the storage elements in the sample and hold circuit. Switches are added to isolate the sample and hold circuit from the column line coupled to the pixel array and to short the front plates of the capacitors together. Activating these switches allows the signals stored in the sample and hold circuit to be transferred downstream without the use of a crowbar switch.
This application is a continuation application of U.S. application Ser. No. 10/413,365, filed Apr. 15, 2003, and claims domestic priority from the same. the complete disclosure of this prior application is incorporated herein by reference.
FIELD OF THE INVENTIONThe invention relates generally to semiconductor imaging devices and in particular to an imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to a CMOS active pixel sensor (APS) imager having an array of pixel cells and to the column circuitry for reading the cells.
BACKGROUND OF THE INVENTIONThere is a current interest in CMOS active pixel imagers for use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to
The photodiode 162 of the 3T pixel cell 150 converts incident photons to electrons which collect at node A. The source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at node A. The signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry when a particular row containing the cell 150 is selected by the row selection transistor 188. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst is selectively coupled through reset transistor 184 to node A. The gate of the reset transistor 184 is coupled to a reset control line 191 which serves to control the reset operation (i.e., Vrst is connected to node A). Vrst may be Vdd. The row select control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source follower transistor 186 and its output is selectively coupled to a column line 170 through the row select transistor 188. Although not shown in
As known in the art, a two step process is used to read a value from pixel 150. During a charge integration period, the photodiode 162 converts photons to electrons which collect at the node A. The charges at node A are amplified by source follower transistor 186 and selectively passed to the column line 170 by the row access transistor 188. During a reset period, node A is reset by turning on the reset transistor 184, such that the reset voltage Vrst is applied to node A and read out to the column line 170 by the source follower transistor 186 through the activated row select transistor 188. As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column lines 170 and the column lines are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines.
As seen in
The operation of the
To transfer Vsig and Vrst through the output stage 354 (
One issue associated with the APS CMOS imaging systems is that of fixed pattern noise, which is type of distortion in the image captured by the imaging system. One source of fixed pattern noise is due to imperfections in the sample and hold circuit. The layout of the sample and hold circuit contributes to the amount of fixed pattern noise. In particular, the crowbar switch in the sample and hold circuit, i.e., 413 in
A sample and hold circuit having a reduced fixed pattern noise is desired.
SUMMARY OF THE INVENTIONThe present invention provides an improved sample and hold readout circuit and method of operation which reduces fixed pattern noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output. This is accomplished by eliminating the crowbar switch between the storage areas in the sample and hold circuit. Additionally, a switch is added further isolating the sample and hold circuit from the column line coupled to the pixel array. In this manner, the signals stored in the sample and hold circuit are transferred downstream by isolating the sample and hold circuit from the global column line and then using the sampling switches SH_R and SH_S to short the front plates of the capacitors together. This has the additional advantage of creating a more symmetrical sample and hold circuit.
These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or other changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention.
The present invention eliminates the crowbar switch and utilizes the sampling switches to short the front plates of the capacitors together when performing a read out from the sample and hold circuit.
An embodiment of the invention is shown and described with reference to
As seen in
The operation of the
To store Vsig on capacitor 620 while the pixel is in the signal sampling phase, a pulse signal SH_S is applied which temporarily closes the switch 612 and couples the desired pixel with the input side of capacitor 620 through the column line 670. The input side of capacitor 618 is also coupled to the Vln voltage through switches 610 and 636. Thus, Vsig is stored on capacitor 620. After Vsig is stored, switch 610 is opened, thereby isolating the input side of capacitor 618 from the desired pixel and the Vln voltage.
After the desired pixel is pulsed by a pixel reset signal, the pixel is in reset signal sampling phase. To store Vrst on capacitor 618, pulse signal SH_R is applied, which temporarily closes the switch 610 and couples the desired pixel with the front side of capacitor 618 through the column line 670. The input side of capacitor 620 is also coupled to the Vln voltage through switches 612 and 636. Thus, Vrst is stored on capacitor 618. After Vrst is stored, switch 612 is opened, thereby isolating the input side of capacitor 620 from the desired pixel and the Vln voltage and switch 652 and 636 are opened, isolating the common node 611 from the column line 670 and Vln voltage. Alternatively, switch 612 remains closed and switches 652 and 636 are opened, thereby isolating the input side of capacitor 620 from the desired pixel and the Vln voltage.
To transfer Vsig and Vrst through the output stage 354 (
The method and apparatus aspects of the invention are embodied in an image device 1140 shown in
While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. Although the embodiments discussed above describe a specific circuit layout with a specific number of transistors, photodiodes, switches, conductive lines, the present invention is not so limited. Furthermore, many of the above embodiments described are shown with respect to the operation of the sample and hold of a desired pixel that is a 3T pixel, the spirit of the invention is not limited to 3T pixels. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the claims.
Claims
1. A sample and hold circuit for an imager, comprising:
- a selection circuit for selectively coupling a common node to a pixel output column line and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals, said selection circuit for selectively uncoupling said common node from said pixel output column line and for selectively coupling said first and second storage elements through said common node to transfer said stored respective pixel output signals to an output stage.
2. The sample and hold circuit of claim 1, wherein said selection circuit further comprises:
- a first switch, disposed between said common node and said column line.
3. The sample and hold circuit of claim 2, wherein said selection circuit further comprises:
- a second switch, disposed between said common node and said first storage element; and
- a third switch, disposed between said common node and said second storage element.
4. The sample and hold circuit of claim 3, wherein said selection circuit selectively couples said common node to a first voltage.
5. The sample and hold circuit of claim 4, wherein said first voltage is a load voltage.
6. (canceled)
7. (canceled)
8. A sample and hold circuit for an imager, comprising:
- a first switch for selectively coupling a common node to an imager array column line;
- a first storage circuit for sampling and holding a first signal from said imager array column line, said first storage circuit having an input side and an output side;
- a second switch for selectively coupling the input side of said first storage circuit to said common node;
- a second storage circuit for sampling and holding a second signal from said imager array column line, said second storage circuit having an input side and an output side; and
- a third switch for selectively coupling the input side of said second storage circuit to said common node.
9. The sample and hold circuit of claim 8, further comprising:
- a fourth switch for selectively coupling the output side of said first storage circuit to an output stage; and
- a fifth switch for selectively coupling the output side of said second storage circuit to said output stage.
10. (canceled)
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14. A sample and hold circuit for an imager, comprising:
- a selection circuit for selectively coupling a common node to an imager column line and for sequentially coupling a first and second storage element to said common node to sample and store respective imager output signals, wherein said selection circuit further comprises:
- a first switch, disposed between said common node and said imager column line;
- a second switch, disposed between said common node and said first storage element;
- a third switch, disposed between said common node and said second storage element; and
- a fourth switch for coupling said common node to a load voltage.
15. The circuit of claim 14, wherein said first and fourth switches being selected.
16. (canceled)
17. (canceled)
18. A sample and hold circuit for an imager, comprising:
- a selection circuit for selectively coupling a common node to an imager column line and for sequentially coupling a first and second storage element to said common node to sample and store respective imager output signals, wherein said selection circuit further comprises:
- a first switch, disposed between said common node and said imager column line;
- a second switch, disposed between said common node and said first storage element;
- a third switch, disposed between said common node and said second storage element;
- a fourth switch for coupling said common node to a load voltage; and
- wherein said second and third switches being sequentially selected when said first switch being selected, said second and third switches being substantially contemporaneously selected when said first switch not being selected.
19. A sample and hold circuit for an imager, comprising:
- a selection circuit for selectively coupling a common node to an imager column line and for sequentially coupling a first and second storage element to said common node to sample and store respective imager output signals, wherein said selection circuit further comprises:
- a first switch, disposed between said common node and said imager;
- a second switch, disposed between said common node and said first storage element;
- a third switch, disposed between said common node and said second storage element; and
- a fourth switch for coupling said common node to a load voltage.
20. The circuit of claim 19, wherein said first and fourth switches being selected.
21. (canceled)
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24. (canceled)
25. (canceled)
26. (canceled)
27. (canceled)
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35. A semiconductor imaging device, comprising:
- a pixel array imager comprising:
- a sample and hold circuit, comprising:
- a selection circuit for selectively coupling a common node to a pixel output and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals.
36. The semiconductor imaging device of claim 35, wherein said selection circuit further comprises:
- a switch, disposed between said common node and said pixel.
37. The semiconductor imaging device of claim 36, wherein said selection circuit further comprises:
- a second switch, disposed between said common node and said first storage element; and
- a third switch, disposed between said common node and said second storage element.
38. The semiconductor imaging device of claim 37, wherein said selection circuit selectively couples said common node to a first voltage.
39. The semiconductor imaging device of claim 38, wherein said first voltage is a load voltage.
40. A processor system, comprising:
- a central processing unit;
- array imager coupled to said central processing unit, said imager comprising:
- a sample and hold circuit, comprising:
- a selection circuit for selectively coupling a common node to a pixel output column line and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals, said selection circuit for selectively uncoupling said common node from said pixel output column line and for selectively coupling said first and second storage elements through said common node to transfer said stored respective pixel output signals to an output stage.
41. The processor of claim 40, wherein said selection circuit further comprises:
- a first switch, disposed between said common node and said column line.
42. The processor of claim 41, wherein said selection circuit further comprises:
- a second switch, disposed between said common node and said first storage element; and
- a third switch, disposed between said common node and said second storage element.
43. The processor of claim 42, wherein said selection circuit selectively couples said common node to a first voltage.
44. The processor of claim 43, wherein said first voltage is a load voltage.
45. (canceled)
46. (canceled)
47. A sample and hold circuit for an imager, comprising:
- a switching circuit for selectively coupling a sample and hold circuit to a pixel output column line and for sequentially coupling first and second storage elements to said pixel output column line through a first and second switch, respectively, to sample and store respective pixel output signals, said switching circuit for selectively uncoupling said sample and hold circuit from said pixel output column line.
48. The sample and hold circuit of claim 47, wherein said switching circuit further comprises a third switch, disposed between said first and second switches and said pixel output column line.
49. The sample and hold circuit of claim 48, further comprising:
- a fourth switch for selectively coupling a first voltage to said first and second storage elements through said second and third switches, respectively.
50. The sample and hold circuit of claim 49, wherein said first voltage is a load voltage.
51. A method of operating a sample and hold circuit in an imaging pixel array, said method comprising:
- selectively connecting a selected imager array column line to said sample and hold circuit;
- selectively coupling said first storage circuit to said selected column line;
- storing a first signal from said selected column line in said first storage circuit;
- selectively coupling said second storage circuit to said selected column line; and
- storing a second signal from said selected column line in said second storage circuit.
52. The method of claim 51, further comprising:
- selectively disconnecting said selected column line from said first storage circuit, after said first signal is stored; and
- selectively disconnecting said selected column line from said second storage circuit, after said second signal is stored.
53. The method of claim 52, further comprising:
- selectively disconnecting said sample and hold circuit from said selected column line, after said first and second signals are stored.
54. The method of claim 53, further comprising:
- selectively contemporaneously coupling input sides of said first and the input side of said second storage circuits while selectively coupling output sides of said first and second storage circuits to an output stage.
55. The method of claim 54, wherein the selective coupling of the said first and second storage circuits to said output stage is controlled by a common signal.
56. The method of claim 55, further comprising the step of initially coupling a clamp voltage to said first and second storage circuits.
57. The method of claim 56, further comprising the step of coupling a load voltage to said first and second storage circuits prior to said storing of said first and said second signals.
Type: Application
Filed: Mar 13, 2008
Publication Date: Sep 18, 2008
Inventor: Giuseppe Rossi (Pasadena, CA)
Application Number: 12/076,084
International Classification: H04N 5/335 (20060101); H04N 3/14 (20060101);