Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.
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The present U.S. Utility patent application claims priority pursuant to 35 U.S.C. §120, as a continuation, to the following U.S. Utility patent application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility patent application for all purposes:
1. U.S. Utility application Ser. No. 11/320,401, entitled “Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth,” (Attorney Docket No. BP4881), filed Dec. 28, 2005, pending, and scheduled to be issued as U.S. Pat. No. 7,598,788 on Oct. 6, 2009, which claims priority pursuant to 35 U.S.C. §119(e) to the following U.S. Provisional Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility patent application for all purposes:
a. U.S. Provisional Application Ser. No. 60/714,814, entitled “Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth,” (Attorney Docket No. BP4881), filed Sep. 6, 2005, now expired.
INCORPORATION BY REFERENCEThe following U.S. Utility patent applications are hereby incorporated herein by reference in their entirety and made part of the present U.S. Utility Patent Application for all purposes:
1. U.S. Utility patent application Ser. No. 09/484,856, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645), filed Jan. 18, 2000, now U.S. Pat. No. 6,424,194 B1, issued on Jul. 23, 2002.
2. U.S. Utility patent application Ser. No. 09/610,905, entitled “Current-controlled CMOS circuits with inductive broadbanding,” (Attorney Docket No. BP1652), filed Jul. 6, 2000, now U.S. Pat. No. 6,340,899 B1, issued on Jan. 22, 2002.
3. U.S. Utility patent application Ser. No. 10/028,806, entitled “Current-controlled CMOS wideband data amplifier circuits,” (Attorney Docket No. BP1817), filed Oct. 25, 2001, now U.S. Pat. No. 6,624,699 B2 issued on Sep. 23, 2003.
BACKGROUND OF THE INVENTION1. Technical Field of the Invention
The invention relates generally to the field of communication devices; and, more particularly, it relates to the field of delay cells that can be implemented within such communication devices.
2. Description of Related Art
Data communication systems have been under continual development for many years. In many broadband data communication system application, variable delay cells are employed. In such applications, it is oftentimes desirable to adjust timing control between various components. One such possible implementation of a delay cell is within the context of a delay locked loop (DLL). A common approach to designing a DLL is to employ a number of delay blocks. In the prior art, each of the individual delay blocks can be undesirably power consumptive. It would be desirable to have a delay block design that is more energy efficient.
For appropriate alignment and control of the various components within a communication system, it is very often desirable to ensure having some means by which the various signal therein can be adjusted to ensure proper alignment and timing. As such, there has been and continues to be a need for better and more efficient means by which delay cells may be implemented within communication systems and within various communication devices within such communication systems.
BRIEF SUMMARY OF THE INVENTIONThe present invention is directed to apparatus and methods of operation that are further described in the following Brief Description of the Several Views of the Drawings, the Detailed Description of the Invention, and the claims. Other features and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.
Various embodiments of the invention provide for ultra high-speed logic circuitry implemented in silicon complementary metal-oxide-semiconductor (CMOS) process technology. A distinction is made herein between the terminology “CMOS process technology” and “CMOS logic.” CMOS process technology as used herein refers generally to a variety of well established CMOS fabrication processes that form a field-effect transistor over a silicon substrate with a gate terminal typically made of polysilicon material disposed on top of an insulating material such as silicon dioxide. CMOS logic, on the other hand, refers to the use of complementary CMOS transistors (n-channel and p-channel, implemented using NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors or PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors) to form various logic gates and more complex logic circuitry, wherein zero static current is dissipated. Embodiments of the invention use current-controlled mechanisms to develop a family of very fast current-controlled CMOS (C3MOS or C3MOS™) logic that can be fabricated using a variety of conventional CMOS process technologies, but that unlike conventional CMOS logic does dissipate static current. C3MOS logic or current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) logic are used herein interchangeably.
Various C3MOS circuit techniques are described in greater detail in commonly-assigned U.S. patent application Ser. No. 09/484,856, now U.S. Pat. No. 6,424,194 B1, entitled “Current Controlled CMOS Logic Family,” by A. Hairapetian, which is hereby incorporated by reference in its entirety for all purposes as indicated above.
Other techniques have been developed to increase the gain-bandwidth product of CMOS circuitry. For example, shunt peaking is one approach that has resulted in improved gain-bandwidth product. Shunt peaking involves putting an inductor in series with the output resistor to expand the bandwidth of the circuit. Such inductive broadbanding technique combined with C3MOS circuitry is described in greater detail in commonly-assigned U.S. patent application Ser. No. 09/610,905, now U.S. Pat. No. 6,340,899 B1, entitled “Current-Controlled CMOS Circuits with Inductive Broadbanding,” by M. Green, which is hereby incorporated by reference in its entirety for all purposes as indicated above.
In commonly-assigned U.S. patent application Ser. No. 10/028,806, now U.S. Pat. No. 6,624,699 B2, entitled “Current-controlled CMOS wideband data amplifier circuits,” by Guangming Yin and Jun Cao, which is hereby incorporated by reference in its entirety for all purposes as indicated above, the current-controlled CMOS wideband data amplifier circuits disclosed therein having expanded bandwidth are designed to achieve such the goal of having a flat frequency response over a very wide frequency range, where maximum bandwidth expansion is achieved by using series inductor peaking with Miller capacitance cancellation technique and shunt inductor peaking in current controlled CMOS (C3MOS or Current-controlled CMOS wideband data amplifier circuits) circuits.
Assuming that the first and second differential transistors are identical, then the first and second series peaking inductors L1 and L2 have the same inductance. A first output resistor R3 has its negative end tied to the drain of the first differential transistor, and has its positive end tied to the negative end of a first shunt peaking inductor L3. A second output resistor R4 has its negative end tied to the drain of the second differential transistor, and has its positive end tied to the negative end of a second shunt peaking inductor L4. The positive ends of the first and second shunt peaking inductors L3 and L4 are tied to the positive supply voltage (shown as VCC).
Preferably, the first and second output resistors R3 and R4 have the same resistance value R, and the first and second shunt peaking inductors L3 and L4 have the same inductances. A first capacitor C1 (which may be referred to as a first Miller cancellation capacitor C1) has its positive end coupled to the drain of the second differential transistor, and has its negative end coupled to the gate of the first differential transistor. A second capacitor C2 (which may be referred to as a second Miller cancellation capacitor C2) has its positive end coupled to the drain of the first differential transistor, and has its negative end coupled to the gate of the second differential transistor. A first output signal OUTP is taken at the drain of the second differential transistor, and the second output signal OUTN is taken at the drain of the first differential transistor.
Input series inductors (L1 and L2) resonate with the capacitance at the input of the differential pair at high frequencies and thus extend the bandwidth of the amplifier. In addition, at high frequencies, the inductors (L1 and L2) act as high impedance chokes between the termination resistors (shown as two series connected 50Ω resistors) and the capacitors and thus also improve the input reflection for the C3MOS wideband data amplifier circuit of this embodiment 100.
In the embodiment 300 of a variable delay cell implemented using a 5-tap FIR filter, a goal is to have a data stream with an equal delay (e.g., Δtn) between each of the various components of the data stream. In the embodiment 300, there are 5 components of the data stream. Typically, this delay (e.g., Δtn) is the same, and the delays of each of these delay cells 310, 320, 330, and 340 may be adjusted together.
Another possible embodiment by which a variable delay cell can be implemented is to add a variable capacitive load at the output of conventional data buffers (e.g., differential pairs). However, there is a fundamental limitation on such an approach. For those circuits whose small-signal transfer function can be approximated by a single-pole response, the bandwidth and delay are directly coupled together. For example, the 10%-90% rise/fall time in response to an input step equals to 0.35/BW (where BW is the −3 dB bandwidth of the small signal response of the circuit). The larger is the delay amount, then the smaller is the bandwidth. As a result, the minimum bandwidth requirement on the delay cell puts an upper limit of the delay amount if such a circuit is employed. On the other hand, the smaller is the delay amount, then the larger is the bandwidth the circuit needs to have, which usually means more power and larger area the delay cell needs to have if a simple single-pole buffer is employed.
For transmission rates of 10 Gbps (Giga-bits per second) or higher, CMOS data buffers generally consume a significant amount of power due to limitations of the technology. In the two-path embodiment 400 of the
The embodiment 400 mixes two types of buffers together: a slow buffer and a fast buffer. The larger delay that is required or desired in a particular application inherently incurs a lower bandwidth in the embodiment 400. The lower bandwidth in such an instance acts as a low pass filter (LPF). This LPF filtering may corrupt the signal undesirably due to the low frequency cut-off. Undesirable inter-symbol Interference (ISI) may also be introduced because of this LPF filtering. In very high speed, broadband application, such effects can significantly reduce overall performance.
Connected to the output of the wideband data buffer having expanded bandwidth (that includes the differential transistor pair M1 and M2, i.e. a wideband differential transistor pair) is a cross-coupled differential pair (that includes the differential transistor pair M3 and M4, i.e. a cross-coupled differential transistor pair) as the regenerative stage for the data. In this embodiment 500, there are therefore two very fast operating blocks [(1) wideband data buffer and (2) cross-coupled differential pair] that operate cooperatively to perform the functionality of a wideband variable delay cell that is appropriate for broadband applications.
To vary the delay, the currents of the buffer stage and the cross-coupled differential pair stage can be adjusted (e.g., using a control block 530). When all the current passes through the buffer stage and the cross-coupled differential pair stage current source is turned off, the circuit behaves just like a wideband data amplifier having expanded bandwidth as described and referenced above (i.e., the embodiment 100 of the
Since the buffer stage of the variable delay cell has very high bandwidth, the delay from input to output at this stage is very small. It is reasonable to assume the delay through the buffer stage is a relatively constant value (denoted as Tb); the delay variation of the delay cell is mostly contributed by the regenerative process of the cross-coupled differential pair stage (denoted as Tr). In the two-step approximation, the signal through the delay cell is divided into two steps. In the first step, the signal Vin is buffered by the input stage and appear at the output after a delay of T0, taking a value of Vm·Vm is equal to the current passing through the buffer stage (Ib) times the load resistance (R). In the second step, the signal Vm at the input of the cross-coupled differential pair goes through the positive feedback of the cross-coupled differential pair and gets regenerated until reaching the value of V0, after a delay of Tr. The voltage, V0, is a fixed value, determined by the total current (I0=Ib+Ir) and load resistance (V0=R·I0).
If it assumed that Ib=x·I0, then Ir=(1−x)·I0. The value of x can be changed between 1 and 0, where x=1 means that all the current is going through the buffer stage. At the output, which is also the input of the cross-coupled differential pair (that includes the differential transistor pair M3 and M4), after T0 of delay vm=x·I0·R. It is noted that the output voltage of a regenerative cross-coupled differential pair increases exponentially with time and is proportional to the initial voltage as indicated below.
V(t)=Vm·e(t/τ)
where τ is the characteristic time constant of the cross-coupled differential pair, which is inversely proportional to the gain of the cross-coupled differential pair. For CMOS transistors, the gain is proportional to the square root of the biasing current in the first order as indicated below.
It is evident that as the current passing through the buffer stage becomes smaller, the delay through the cross-coupled differential pair stage becomes bigger. The total delay through the delay cell is T=Tb+Tr. Thus by changing the current distribution between the buffer stage (including the differential transistor pair M1 and M2) and cross-coupled differential pair stage (including the differential transistor pair M3 and M4) (i.e., which involves changing the value of x), the amount of the delay can be readily adjusted.
This control of the two currents, Ib and Ir and their relationship, may be performed using a control block (e.g., control block 530 in the embodiment 500 of the
As the value of x approaches 1, then the total delay a variable delay cell (e.g., the embodiment 500 of the
Various embodiments of the invention presented herein provide for a large amount of delay to be incurred (which is selectable and variable, as desired in any of a wide variety of applications) with a minimal amount of signal quality degradation (i.e., minimal or no ISI).
One of many advantages of this novel design is that all the bandwidth extension techniques as referenced above with respect to a wideband data amplifier circuit having expanded bandwidth can be readily applied to the variable delay cell. In the embodiment 500 of
By eliminating the double path (as depicted in the embodiment 400 of the
From the embodiment 500 of the
In summary, a fully differential current-controlled CMOS (C3MOS) integrated wideband delay cell is presented herein. At the buffer stage, bandwidth extension techniques such as shunt peaking, series inductive peaking can be readily applied to increase the range of the flat frequency response. A cross-coupled differential pair stage is added to the output of the buffer to add delay from input to output through the regenerative process of the cross-coupled differential transistor pair connected in a positive feedback configuration. The delay can be adjusted by varying the current distribution between the buffer stage and the cross-coupled differential pair stage. The integrated delay cell can then accommodate a large amount of delay while at the same time maintain a high bandwidth for the data path, without adding load to the input and without adding power consumption.
It is also noted that the methods described within the preceding figures can also be performed within any appropriate system and/or apparatus design (communication systems, communication transmitters, communication receivers, communication transceivers, and/or functionality described therein) without departing from the scope and spirit of the invention.
In view of the above detailed description of the invention and associated drawings, other modifications and variations will now become apparent. It should also be apparent that such other modifications and variations can be effected without departing from the spirit and scope of the invention.
Claims
1. A circuit, comprising:
- a first differential transistor having a first source, a first gate that is operative to receive a first differential input, and a first drain;
- a second differential transistor having a second source that is connected to the first source, a second gate that is operative to receive a second differential input, and a second drain;
- a third differential transistor having a third source, a third gate, and a third drain;
- a fourth differential transistor having a fourth source that is connected to the third source, a fourth gate, and a fourth drain;
- wherein the first drain, the third drain, and the fourth gate are connected at a first node that is a first differential output;
- wherein the second drain, the fourth drain, and the third gate are connected at a second node that is a second differential output;
- a first variable current source transistor having a fifth drain connected to the connected first source and second source, having a fifth gate, and having a fifth source that is grounded;
- a second variable current source transistor having a sixth drain connected to the connected third source and fourth source, having a sixth gate, and having a sixth source that is grounded; and
- a control module that is operative to adjust a delay of the circuit by adjusting a first DC bias voltage provided to the fifth gate to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to the sixth gate to set a second DC bias current in the second variable current source transistor.
2. The circuit of claim 1, wherein:
- the control module that is operative to keep a sum of the first DC bias current and the second DC bias current constant.
3. The circuit of claim 1, further comprising:
- a first inductor connected to the first gate; and
- a second inductor connected to the second gate.
4. The circuit of claim 1, further comprising:
- a first impedance component whose ends are connected to the first drain and to a power supply voltage of the circuit, respectively; and
- a second impedance component whose ends are connected to the second drain and to the power supply voltage of the circuit, respectively.
5. The circuit of claim 4, wherein:
- the first impedance component includes a first output resistor and a first inductor connected in series; and
- the second impedance component includes a second output resistor and a second inductor connected in series.
6. The circuit of claim 1, further comprising:
- a first capacitor whose ends are connected to the first drain and to the second gate, respectively; and
- a second capacitor whose ends are connected to the second drain and to the first gate, respectively.
7. The circuit of claim 1, wherein:
- the sum of the first DC bias current and the second DC bias current being constant keeps a DC level of the first differential output and the second differential output constant.
8. The circuit of claim 1, wherein:
- the delay of the circuit is a function of a ratio of the first DC bias current divided by the sum of the first DC bias current and the second DC bias current.
9. The circuit of claim 1, wherein:
- the circuit is one delay cell of a plurality of delay cells implemented within an n-tap finite impulse response (FIR) filter.
10. The circuit of claim 1, further comprising:
- a flip-flop (FF); and wherein:
- the first node and the second node are connected to an input of a FF; and
- the FF is operative to receive a clock signal.
11. The circuit of claim 1, wherein:
- the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source, and the second variable current source are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.
12. A circuit, comprising:
- a first differential transistor having a first source, a first gate, and a first drain;
- a second differential transistor having a second source that is connected to the first source, a second gate, and a second drain;
- a first inductor whose ends are connected to a first differential input and to the first gate, respectively;
- a second inductor whose ends are connected to a second differential input and to the second gate, respectively;
- a third differential transistor having a third source, a third gate, and a third drain;
- a fourth differential transistor having a fourth source that is connected to the third source, a fourth gate, and a fourth drain;
- wherein the first drain, the third drain, and the fourth gate are connected at a first node that is a first differential output;
- wherein the second drain, the fourth drain, and the third gate are connected at a second node that is a second differential output;
- a first variable current source transistor having a fifth drain connected to the connected first source and second source, having a fifth gate, and having a fifth source that is grounded;
- a second variable current source transistor having a sixth drain connected to the connected third source and fourth source, having a sixth gate, and having a sixth source that is grounded; and
- a control module that is operative to: adjust a delay of the circuit by adjusting a first DC bias voltage provided to the fifth gate to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to the sixth gate to set a second DC bias current in the second variable current source transistor; the control module that is operative to keep a sum of the first DC bias current and the second DC bias current constant.
13. The circuit of claim 12, further comprising:
- a first impedance component whose ends are connected to the first drain and to a power supply voltage of the circuit, respectively; and
- a second impedance component whose ends are connected to the second drain and to the power supply voltage of the circuit, respectively.
14. The circuit of claim 13, wherein:
- the first impedance component includes a first output resistor and a first inductor connected in series; and
- the second impedance component includes a second output resistor and a second inductor connected in series.
15. The circuit of claim 12, further comprising:
- a first capacitor whose ends are connected to the first drain and to the second gate, respectively; and
- a second capacitor whose ends are connected to the second drain and to the first gate, respectively.
16. The circuit of claim 12, wherein:
- the sum of the first DC bias current and the second DC bias current being constant keeps a DC level of the first differential output and the second differential output constant.
17. The circuit of claim 12, wherein:
- the delay of the circuit is a function of a ratio of the first DC bias current divided by the sum of the first DC bias current and the second DC bias current.
18. A circuit, comprising:
- a first differential transistor having a first source, a first gate that is operative to receive a first differential input, and a first drain;
- a second differential transistor having a second source that is connected to the first source, a second gate that is operative to receive a second differential input, and a second drain;
- a first capacitor whose ends are connected to the first drain and to the second gate, respectively;
- a second capacitor whose ends are connected to the second drain and to the first gate, respectively;
- a third differential transistor having a third source, a third gate, and a third drain;
- a fourth differential transistor having a fourth source that is connected to the third source, a fourth gate, and a fourth drain;
- wherein the first drain, the third drain, and the fourth gate are connected at a first node that is a first differential output;
- wherein the second drain, the fourth drain, and the third gate are connected at a second node that is a second differential output;
- a first variable current source transistor having a fifth drain connected to the connected first source and second source, having a fifth gate, and having a fifth source that is grounded;
- a second variable current source transistor having a sixth drain connected to the connected third source and fourth source, having a sixth gate, and having a sixth source that is grounded; and
- a control module that is operative to: adjust a delay of the circuit by adjusting a first DC bias voltage provided to the fifth gate to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to the sixth gate to set a second DC bias current in the second variable current source transistor; and keep a sum of the first DC bias current and the second DC bias current constant thereby keeping a DC level of the first differential output and the second differential output constant; and wherein:
- the delay of the circuit is a function of a ratio of the first DC bias current divided by the sum of the first DC bias current and the second DC bias current.
19. The circuit of claim 18, further comprising:
- a first impedance component whose ends are connected to the first drain and to a power supply voltage of the circuit, respectively; and
- a second impedance component whose ends are connected to the second drain and to the power supply voltage of the circuit, respectively.
20. The circuit of claim 18, wherein:
- the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source, and the second variable current source are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.
Type: Application
Filed: Oct 1, 2009
Publication Date: Jan 28, 2010
Applicant: BROADCOM CORPORATION (IRVINE, CA)
Inventor: Jun Cao (Irvine, CA)
Application Number: 12/571,553
International Classification: H03H 11/26 (20060101);