Abstract: A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.

Abstract: A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

Abstract: A system is disclosed that includes memory resources and one or more processing components coupled to the one or more memory resources. At least one of the memory resources stores a basic input/output system (BIOS). The one or more processing components are coupled to the memory resources to run a program for operating a point-of-sale (POS) terminal. The program enables a user to provide an input to open a cash drawer. A controller circuit receives a signal from the BIOS when the user provides the input and generates a pulse signal having a predetermined duration to cause a voltage signal to be transmitted to a solenoid of the cash drawer. The voltage signal causes the solenoid to change states in order to open the cash drawer.

Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.

Abstract: An analog-to-digital converter includes a gain amplification unit configured to receive a pixel signal at a first node and to amplify a gain of the pixel signal, a first capacitor connected between the first node and a second node, an amplifier configured to receive and amplify a signal output from the gain amplification unit and the first capacitor, and a conversion circuit configured to convert an output signal of the amplifier to a digital signal based on a reference signal and output the digital signal as a first output signal.

Abstract: An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: A digitally controlled delay device includes at least one delay generating gate device, whose propagation delay is controlled by limiting operating current by means of a tail transistor that is controlled by its gate voltage, a gate control voltage control means for controlling the current limiting transistor gate voltage, and a bank of digitally controlled MOSFET transistors in parallel configuration, and the digital control is adapted to switch the transistors to off and to diode mode connection, current feeding means to feed current through the bank of MOSFET transistors, and the voltage over the bank of parallel transistors is used for gate source control voltage of the tail transistors.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.

Abstract: A differential delay line includes a series connection of a plurality of differential delay stages. Each differential delay stage includes a first delay element and a second delay element. The first delay element has a first input, a second input and an output. The second delay element has a first input, a second input and an output. The output of the first delay element of an n-th differential delay stage of the plurality of differential delay stages is coupled to an input of the second delay element of an (n+m)-th differential delay stage of the plurality of differential delay stages, wherein m is an even natural number larger than or equal to two.

Abstract: Buffers, integrated circuits, apparatuses, and methods for adjusting drive strength of a buffer are disclosed. In an example apparatus, the buffer includes a driver. The driver includes a pull-up circuit coupled to a supply voltage node and an output node, and also includes a pull-down circuit coupled to a reference voltage node and the output node. A drive adjust circuit is coupled to at least one of the pull-up circuit and the pull-down circuit, with the drive adjust circuit configured to receive a feedback signal and, based at least in part on the feedback signal, adjust a current conducted through the at least one of the pull-up and pull-down circuits.

Abstract: High speed serial link techniques are provided. A system applying the high speed serial link technique comprises a relay unit and an amplifier. The relay unit receives a first pair of differential signals provided by a high speed transmitter of a first device, and provides the amplifier with at least one signal that is generated based on the first pair of differential signals. The amplifier amplifies and converts the signal provided by the relay unit to a second pair of differential signals to be received by a high speed receiver of a second device.

Abstract: Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.

Abstract: In one embodiment, the differential amplifier (DA) includes a first inverter inverting a first input signal and outputting the inverted first input signal to a current supply controller and a current drain controller. A second inverter inverts the first input signal and outputs the inverted first input signal as an output signal of the DA. The current supply controller supplies current to the first and second inverters in response to the inverted first input signal output from the first inverter during a first period. The current drain controller drains current from the first and second inverters in response to the inverted first input signal output from the first inverter during a second period. The output signal of the DA and the first input signal have differential phases with respect to each other and oscillate between logic high and low levels during the first period and the second period.

Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

Abstract: An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

Abstract: Techniques and corresponding circuits for achieving programmable delay of a current mode logic delay buffer are provided. The techniques provide for incremental delay with substantially equal increments. Delay may be achieved through the use of a circuit arrangement that allows biasing current to be controlled effect the response time of the circuit by digital control.

Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a current source-connected transistor. The control circuit converts an oscillator input signal into bias control signals that in turn control the effective resistance of the symmetric loads such that delays through the delay cells are a function of the input signal. The control circuit uses a symmetric load replica in a control loop to control the level shift circuits of the delay cells such that the oscillating delay cell output signals have a constant amplitude. In a first advantageous aspect, due to the constant amplitude, the oscillator is operable over a wide frequency range. In a second advantageous aspect, the oscillator input signal to output signal oscillation frequency has a substantially linear relationship.

Abstract: A delay circuit includes current sources, switches, a transistor switch, a charging unit and a comparator. Each of the switches is provided for receiving an enable signal to activate and convey one of the current sources. The transistor switch is activated for pulling down voltage of an operating node coupled to the switches. The charging unit provides an operating voltage for the operating node based on one of the current sources when the transistor switch is deactivated and one of the switches is activated to convey one of the current sources to the charging unit. The comparator is provided for comparing the operating voltage with a reference voltage.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal.

Abstract: An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.

Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

Abstract: A delay apparatus of a synchronizing circuit and a method of controlling the same are provided. In order to improve jitter characteristics, the delay apparatus includes delay units delaying input signal by variable delaying devices according to, a predetermined voltage, and a current amount control unit that changes a unit variation amount of the delay.

Abstract: A delay cell for use in a voltage controlled oscillator includes a differential amplifier having a pair of outputs, a common source resistive element supplying current to said differential amplifier, a varactor arrangement between the outputs having a control input, and a pair of load resistive elements connected to the respective outputs. The delay cell has a simple design, a small die area, low power dissipation, constant amplitude of oscillation versus control voltage, and a Figure of Merit (FOM) comparable to that of LC oscillators.

Abstract: A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.

Abstract: Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

Abstract: A system and method for asynchronous triggering in a waveform generator comprising a DAC sample clock for generating DAC sample clock signal. The system includes a sequencer clock for generating a sequencer clock signal having a frequency of 1/N of the DAC sample clock. The system also includes an output data generator having I outputs to receive a waveform data stream of samples shifted into the data generator at the rate of the sequencer clock signal. An output multiplexer coupled receives samples from each of the I outputs of the output data generator and outputs the samples as a multiplexed data stream to the DAC. A triggering system receives an asynchronous trigger and splits the signal into an integer multiple M trigger inputs, each trigger input delayed by a DAC sample clock cycle. A shift controller determines a trigger position based on the trigger inputs and shifts a different waveform data stream into the data generator in accordance with the trigger position.

Abstract: A differential amplifier circuit for use in a ring oscillator includes first and second MOS transistors to each source of which an operating power source voltage is applied, and which individually respond to first and second input signals with mutually contrary phases applied to gates thereof; cross-coupled first and second-stage transistors of which each drain-source channel is connected between each drain of the first and second MOS transistors and a ground voltage level; a first variable resistance, which is connected between a drain of the first MOS transistor cross-connected to a second gate of the cross-coupled second-stage transistors, and a first gate of the cross-coupled first-stage transistors, and which is controlled by the operating power source voltage applied to a gate thereof; and a second variable resistance, which is connected between a drain of the second MOS transistor cross-connected to a second gate of the cross-coupled first-stage transistors, and a first gate of the cross-coupled second

Abstract: A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.

Abstract: A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A differential oscillator circuit, including an oscillator having a first side and a second side and bias circuitry for applying a bias voltage to the first and second sides of the oscillator wherein the bias circuitry is arranged such that, upon start-up, the bias voltage is not applied to the second side of the oscillator until after the first side of the oscillator by a delay period.

Abstract: A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

Abstract: A device for converting an input signal having a bipolar pulse with a positive part and a negative part of same duration, into a difference signal includes a delay member with an input for receiving the input signal and an output. The delay member delays the input signal in order to obtain a delayed signal and outputs the delayed signal to the output. The device further includes a differential amplifier with a first input for receiving the input signal, a second input for receiving the delayed signal, and an output for outputting the difference signal formed from the input signal and the delayed signal.

Abstract: A ring-type voltage-controlled oscillator with a good duty cycle for use in a PLL frequency synthesizer. The delay cell circuit used in the ring-type VCO comprises two first inverters, two resistance units, and a differential delay circuit. The inverters receive respective differential input signals and generate respective differential signals to resistance units. The differential delay circuit is coupled to the resistance units, generating differential output signals which are a delayed version of the differential input signals. The resistance units have a resistance value adjusted according to a resistance control voltage for controlling the strength of inverters so as to alter the time delay of the first and second differential output signals.

Abstract: A first PMOS transistor is connected between a supply terminal of a power supply voltage VCC and a connection node MON. A first NMOS transistor and a second NMOS transistor are connected between the connection node MON and ground. The first PMOS transistor and the first NMOS transistor are driven by an input signal. The second NMOS transistor is driven by a constant current IREF. In cooperation with the first NMOS transistor, the second NMOS transistor discharges the charge across a capacitor C1 connected to the connection node MON. A differential amplifier compares a potential at the connection node MON with a potential depending upon the constant current IREF, and outputs a result of the comparison.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: The voltage comparator of the present invention comprises a sense amplifier connected to a latch. The sense amplifier has a first input terminal for connecting to the input voltage under consideration and a second input terminal for connecting to the reference voltage. The sense amplifier generates two voltages of opposite logic values (i.e., high or low). A latch accepts these two voltages and generates an output voltage that is indicative of whether the voltage under consideration is higher or lower than the reference voltage. In another embodiment, a signal conditioning circuit is used to reduce the transients in the input voltage under consideration and perform level shifting function.

Abstract: Variable delay circuits and methods for delaying a waveform by an adjustable time delay are disclosed herein. One such variable delay circuit comprises a delay range limitation circuit having a first differential input, a first differential output, and a second differential output. The first differential input is configured to receive an input waveform. The first differential output is configured to output the waveform with a maximum delay, and the second differential output is configured to output the waveform with a minimum delay. The variable delay circuit further comprises a delay mixing circuit having second and third differential inputs, first and second control inputs, and a third differential output. The second differential input is connected to the first differential output. The third differential input is connected to the second differential output. The first and second control inputs are configured to receive control voltages V1 and V2, which are related to a selected time delay.

Abstract: A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.

Abstract: A voltage-controlled oscillator design is disclosed that provides greater tuning range than a prior art differential amplifier design using “varactor” diodes. The design employs CMOS capacitors to replace varactor diodes. The CMOS capacitors are formed from PMOS transistors in which the drain of the transistor is electrically connected to the source of the same transistor, so that voltage-dependant capacitors are formed between the gate-to-source terminals and the gate-to-drain terminals of the PMOS transistor. Secondly, the monolithic inductors employed in the prior art are replaced by “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor, where the potential at the drain of the NMOS transistor is held below that of the second terminal of the resistor by at least the threshhold, or turn-on voltage, of the transistor. The resistor/transistor combination acts inductively at the frequency of oscillation of interest.

Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

Abstract: The ring oscillator circuit is made by connecting K units of inverter circuits U11, U12, . . . , U1K in a ring shape. The inverter circuit U11 comprises a CMOS inverter IV1 which includes MOS transistors MP4 and MN4, a P-channel MOS transistor MP3 which functions as the current source for a CMOS inverter IV1, an N-channel MOS transistor MN3 which functions as the current source for a CMOS inverter IV1, and a CMOS inverter IV2 which is connected in parallel to the CMOS inverter IV1 and includes MOS transistors MP5 and MN5.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.