METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF
Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
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This application is a Divisional of U.S. patent application Ser. No. 11/950,741, filed Dec. 5, 2007 and allowed on Mar. 23, 2011.
BACKGROUND1. Technical Field
The disclosure relates generally to patterning of semiconductor structure in complementary metal oxide semiconductor (CMOS) circuits fabrication, and more particularly, to method of enhancing a patterned hard mask.
2. Background Art
In the current state of the art, continued complimentary metal oxide semiconductor (CMOS) scaling has resulted in high density CMOS circuitry. Optical effects in the printing of patterns onto substrates of semiconductors for CMOS circuitry fabrication lead to rounding and dimensional reduction at the ends of printed lines. Often, the rounding and dimensional reduction exacerbates the effectiveness of device and circuit operations in a densely packed circuitry. This is demonstrated in 45 nm static random access memory (SRAM) designs at the active area (RX) and polycrystalline layers.
Crystallographic etching has been recognized as a means for enhancing printed patterns at the RX level. The use of this type of etching technique requires a monocrystalline layer. However, as most semiconductor structures involve non-crystalline and polycrystalline layers, the use of crystallographic etching for such enhancement purposes cannot be applied directly to every level of semiconductor fabrication.
SUMMARYMethod of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
A first aspect of the disclosure provides a method for patterning a semiconductor structure comprising: bonding a monocrystalline layer to a protective layer disposed on the semiconductor structure; lithographically patterning the monocrystalline layer to form a hard mask; applying crystallographic etching to enhance the patterned hard mask; and etching the protective layer according to the enhanced patterned hard mask.
A second aspect of the disclosure provides a semiconductor structure comprising: at least one composite layer formed on a substrate, the composite layer including discrete blocks of different materials, wherein the discrete blocks are defined by straight edges.
A third aspect of the disclosure provides a semiconductor structure comprising: a substrate; and multiple composite layers, wherein at least one of the multiple composite layers is disposed on the substrate, wherein each of the multiple composite layers includes a plurality of discrete blocks of different material, wherein each discrete block is defined by straight edges.
These and other features of the present disclosure are designed to solve the problems herein described and/or other problems not discussed.
Various aspects of the disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings that depict different embodiments of the disclosure, in which:
It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
DETAILED DESCRIPTIONEmbodiments depicted in the drawings in
The top view illustrated in
As shown in
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The method according to the disclosure may be repeated to form a semiconductor structure 20 (
The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the scope of the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
Claims
1. A semiconductor structure comprising:
- at least one composite layer formed on a substrate, the composite layer including discrete blocks of different materials, wherein the discrete blocks are defined by straight edges.
2. The semiconductor structure of claim 1, wherein each of the straight edges are substantially parallel to an adjacent straight edge.
3. The semiconductor structure of claim 2, wherein each of the straight edges and an adjacent straight edge are separated at a substantially constant spacing.
4. The semiconductor structure of claim 1, wherein each of the straight edges meets an adjacent straight edge to form a substantive right-angle.
5. The semiconductor structure of claim 1, wherein the discrete blocks have a thickness in a range from approximately 1 nm to approximately 100 nm.
6. The semiconductor structure of claim 1, wherein each of the straight edges meets at an adjacent straight edge to form an angle selected from one of a 45° angle, a 60° angle, and a 90° angle.
7. The semiconductor structure of claim 1, wherein the different materials includes one selected from a group consisting of: a non-crystalline material, a monocrystalline material, a polycrystalline material and a combination thereof.
8. The semiconductor structure of claim 7, wherein the different materials include a gate oxide material.
9. The semiconductor structure of claim 8, wherein the gate oxide material is disposed directly above the at least one shallow trench isolation (STI) region and the at least one pad oxide region.
10. The semiconductor structure of claim 9, wherein the at least one shallow trench isolation (STI) region and at least one pad oxide region are incorporated in the substrate.
11. The semiconductor structure of claim 7, wherein the different materials include one selected from a group consisting of: silicon nitride, doped oxide, silicon-germanium, borosilicate glass (BSG), borophosphosilicate glass (BPSG), and a combination thereof.
12. A semiconductor structure comprising:
- a substrate; and
- multiple composite layers,
- wherein at least one of the multiple composite layers is disposed on the substrate,
- wherein each of the multiple composite layers includes a plurality of discrete blocks of different material,
- wherein each discrete block is defined by straight edges.
13. The semiconductor structure of claim 12, wherein the straight edges form an angle selective to a monocrystalline material used in crystallographic etching.
14. The semiconductor structure of claim 13, wherein the angle includes one of a 45° angle, a 60° angle, and a 90° angle.
15. The semiconductor structure of claim 12, wherein the straight edges are substantially parallel.
16. The semiconductor structure of claim 12, wherein the discrete blocks have a thickness in a range from approximately 1 nm to approximately 100 nm.
17. The semiconductor structure of claim 12, wherein the different materials include one selected from a group consisting of: silicon nitride, doped oxide, silicon-germanium, borosilicate glass (BSG), borophosphosilicate glass (BPSG), silicon dioxide (SiO2), silicoxynitride, hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and a combination thereof.
18. A semiconductor structure comprising:
- a substrate; and
- multiple composite layers,
- wherein at least one of the multiple composite layers is disposed on the substrate,
- wherein each of the multiple composite layers includes a plurality of discrete blocks of different material,
- wherein each discrete block is defined by substantially parallel straight edges that form an angle selective to a monocrystalline material used in crystallographic etching.
19. The semiconductor structure of claim 18, wherein the angle includes one of a 45° angle, a 60° angle, and a 90° angle.
20. The semiconductor structure of claim 18, wherein the discrete blocks have a thickness in a range from approximately 1 nm to approximately 100 nm.
Type: Application
Filed: May 5, 2011
Publication Date: Sep 8, 2011
Patent Grant number: 8362531
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Thomas W. Dyer (Pleasant Valley, NY), James J. Toomey (Poughkeepsie, NY)
Application Number: 13/102,007
International Classification: H01L 29/06 (20060101);