Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

Abstract: A micromechanical apparatus and a corresponding production method are described. The micromechanical apparatus encompasses a base substrate having a front side and a rear side; and a cap substrate, at least one surrounding trench having non-flat side walls being embodied in the front side of the base substrate; the front side of the base substrate and the trench being coated with at least one metal layer; the non-flat side walls of the trench being covered nonconformingly with the metal so that they do not form an electrical current path in a direction extending perpendicularly to the front side; and a closure, in particular a seal-glass closure, being embodied in the region of the trench between the base substrate and the cap substrate.

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Abstract: A method for transferring semiconductor bodies and a semiconductor chip are disclosed.

Abstract: An electronic component mounting substrate includes an insulating substrate having a rectangular shape in a plan view of the electronic component mounting substrate, the insulating substrate including a mounting portion on a principal face thereof for mounting an electronic component; and first via conductor groups each including first via conductors and second via conductor groups each including second via conductors, the first via conductors and the second via conductors penetrating through the insulating substrate in a thickness direction thereof, a number of the second via conductors being larger than that of the first via conductors, the mounting portion, the first via conductor groups, and the second via conductor groups being disposed so as not to overlap each other in a transparent plan view of the electronic component mounting substrate, the first via conductor groups being located between the mounting portion and the second via conductor groups, respectively.

Abstract: A display apparatus including a substrate including a display area and a peripheral area outside the display area, a first insulating layer over the substrate in the display area and the peripheral area, the first insulating layer including a plurality of first contact holes located in the display area, a plurality of second contact holes located in the peripheral area, and a plurality of dummy contact holes located between the plurality of first contact holes and the plurality of second contact holes, first wirings filling the plurality of first contact holes, second wirings filling the plurality of second contact holes, and a second insulating layer covering the first wirings and the second wirings and filling the plurality of dummy contact holes.

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a substrate temperature from about 400 degrees Celsius to about 700 degrees Celsius, flowing a boron-containing gas mixture into the processing volume and generating an RF plasma in the processing volume to deposit a boron-carbon film on the heated substrate, wherein the boron-carbon film has an elastic modulus of from about 200 to about 400 GPa and a stress from about ?100 MPa to about 100 MPa.

Abstract: In a method of aligning wafers, a second wafer having at least one second alignment key may be arranged over a first wafer having at least one first alignment key. At least one alignment hole may be formed by passing through the second wafer to expose the second alignment key and the first alignment key. The first wafer and the second wafer may be aligned with each other using the first alignment key and the second alignment key exposed through the alignment hole. Thus, the first alignment key and the second alignment key exposed through the alignment hole may be positioned at a same vertical line to accurately align the first wafer with the second wafer.

Abstract: Embodiments disclosed herein generally related to system for forming a semiconductor structure. The processing chamber includes a chamber body, a substrate support device, a quartz envelope, one or more heating devices, a gas injection assembly, and a pump device. The chamber body defines an interior volume. The substrate support device is configured to support one or more substrates during processing. The quartz envelope is disposed in the processing chamber. The quartz envelope is configured to house the substrate support device. The heating devices are disposed about the quartz envelope. The gas injection assembly is coupled to the processing chamber. The gas injection assembly is configured to provide an NH3 gas to the interior volume of the processing chamber. The pump device is coupled to the processing chamber. The pump device is configured to maintain the processing chamber at a pressure of at least 10 atm.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an insulating film, a first interconnect, a conductor, and a frame-shaped portion. The insulating film is provided on the semiconductor layer. The first interconnect is provided on the insulating film. The conductor extends through the insulating film and electrically connects the semiconductor layer and the first interconnect. The frame-shaped portion extends through the insulating film and is provided in a second region different from a first region, the conductor being provided in the first region. The frame-shaped portion protrudes from a surface of the insulating film on which the first interconnect is provided.

Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

Abstract: The invention relates to a precursor composition containing a mixture of a Group IV organic compound represented by Formula 19 and any one compound selected from an organic aluminum compound represented by Formula 1, an organic gallium compound represented by Formula 7, or an organic germanium compound represented by Formula 16, and a method for forming a thin film by using the precursor composition.

Abstract: According to various embodiments, an electronic device may include a conductive bracket including an opening in at least part of the bracket, a display disposed on one surface of the bracket, a battery disposed on another surface of the bracket to face at least part of the opening, an antenna disposed within a specified range of the bracket and configure to output a signal of a first frequency band, and a conductive member comprising conductive material electrically coupled to the bracket by crossing at least part of the opening, wherein the opening is divided into a plurality of openings, to adjust resonance of a second frequency band of the opening generated by the signal output from the antenna.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure. The method includes forming third spacers over second sidewalls of the second spacers. The method includes removing the filling layer and the second spacers.

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.

Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract: A method of forming a semiconductor film at pressure between 10?5 atm and 10 atm in the presence of a substrate includes (i) providing a precursor material in a reaction container; (ii) arranging the substrate on the reaction container such that a conductive surface of the substrate is facing towards the precursor material; and (iii) conducting a heat treatment to deposit a semiconductor layer on the conductive surface of the substrate. A semiconductor film is obtained from this method and a device comprising such semiconductor film is also provided.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Abstract: A system and method for facilitating modifying a runtime application behavior and/or functionality of a networked software application, whereby UI-driven data model modifications effectively propagate back to the UI of the runtime application. The example method includes employing the runtime user interface display screen to present one or more indicators for one or more customizable user interface features of the runtime user interface display screen; generating one or more signals based upon user input, wherein the user input indicates a modification to be made to the one or more customizable user interface features; initiating one or more changes to a computing object and data model associated with the computing object in accordance with the one or more signals; and displaying a modified user interface display screen in accordance with the one or more changes.

Abstract: The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Abstract: The invention provides a memory device. The memory device includes a substrate, a plurality of first wires, a plurality of etch-stop layers, a dielectric layer, and a plurality of vias. The substrate has a plurality of first regions and a plurality of second regions arranged in a staggered manner along a first direction. The first wires are embedded in the substrate and extended along the first direction. The first wires include a conductive layer and a cap layer located on the conductive layer, and the upper surface of the cap layer has a groove. The etch-stop layers are located on the cap layer and filled in the groove. The dielectric layer is located on the substrate and has a plurality of via openings in the first regions. The via openings expose the substrate and the etch-stop layer. The vias are filled in the via openings and electrically connected to the substrate. The invention further provides a manufacturing method of a memory device.

Abstract: A compensating balance spring for a thermally compensated sprung balance resonator including a core formed from at least one non-metallic material. The core is partially coated with at least one layer which is moisture proof to render the balance spring less sensitive to climatic variations.

Abstract: A compensating balance spring for a thermally compensated sprung balance resonator including a core formed from at least one non-metallic material. The core is entirely coated with a layer which is moisture proof to render the balance spring less sensitive to climatic variations. The compensating balance spring can be applied to timepieces.

Abstract: The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Abstract: The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Abstract: An organic light-emitting display apparatus including a substrate; a thin-film transistor (TFT) arranged on the substrate; a black matrix located between the substrate and the TFT; a pixel electrode, which is located between the substrate and the TFT and having edge portions covered by the black matrix; an insulation layer, which covers the TFT and opens the top surface of the pixel electrode; an organic emission layer, which is arranged on the pixel electrode; and a counter electrode, which is arranged on the organic emission layer.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.

Abstract: A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.

Abstract: The yield of a peeling process is improved. A peeling apparatus includes a structure body with a convex surface and a stage with a supporting surface which faces the convex surface. The structure body can hold a first member of a process member between the convex surface and the supporting surface. The stage can hold a second member of the process member. The radius of curvature of the convex surface is less than the radius of curvature of the supporting surface. The linear velocity of the convex surface is greater than or equal to the speed of a rotation center of the structure body passing the stage. The first member is wound along the convex surface to be separated from the second member.

Abstract: Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.

Abstract: A semiconductor structure having micro-electro-mechanical system (MEMS) devices is provided. One of the MEMS devices includes a substrate having a first region and a second region; a membrane structure formed in the first region and positioned correspondingly to a cavity of the substrate; a logic device formed in the second region, and electrically connected to the membrane structure; an interconnection structure formed in the second region, and the interconnection structure formed on the substrate and covering the logic device; and an etching stop layer formed in the second region, and the etching stop layer formed on the interconnection structure and including a nitride layer and a carbon-containing layer formed on the nitride layer. Also, a variation in resonant frequencies of the MEMS devices on the entire wafer is less than 10%.

Abstract: A printed circuit board (PCB) includes an insulating substrate, a plurality of copper foil pattern layers and a plurality of insulating adhesive sheets sequentially stacked on an upper side of the insulating substrate and a lower side of the insulating substrate, an inductor included in the copper foil pattern layer disposed on the upper side of the insulating substrate, a grounding element included in the copper foil pattern layer disposed on the lower side of the insulating substrate, and a single through hole penetrating the insulating substrate and the insulating adhesive sheets. The single through hole is disposed between the inductor and the grounding element.

Abstract: An organic light-emitting display apparatus including a substrate; a thin-film transistor (TFT) arranged on the substrate; a black matrix located between the substrate and the TFT; a pixel electrode, which is located between the substrate and the TFT and having edge portions covered by the black matrix; an insulation layer, which covers the TFT and opens the top surface of the pixel electrode; an organic emission layer, which is arranged on the pixel electrode; and a counter electrode, which is arranged on the organic emission layer.

Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract: A single-phase multi-element film constituted by at least four elements is formed on a substrate by plasma-enhanced atomic layer deposition (PEALD) conducting one or more process cycles. Each process cycle includes: (i) forming an integrated multi-element layer constituted by at least three elements on a substrate by PEALD using at least one precursor; and (ii) treating a surface of the integrated multi-element layer with a reactive oxygen, nitrogen, and/or carbon in the absence of a precursor for film formation so as to incorporate at least one new additional element selected from oxygen, nitrogen, and carbon into the integrated multi-element layer.

Abstract: The present invention provides a metallic material for electronic components having a low degree of whisker formation and a high durability, and connector terminals, connectors and electronic components using the metallic material. The metallic material for electronic components includes: a base material; on the base material, an lower layer constituted with one or two or more selected from the group consisting of Ni, Cr, Mn, Fe, Co and Cu; on the lower layer, an upper layer constituted with an alloy composed of one or both of Sn and In (constituent elements A) and one or two or more of Ag, Au, Pt, Pd, Ru, Rh, Os and Ir (constituent elements B), wherein the thickness of the lower layer is 0.05 ?m or more; the thickness of the upper layer is 0.005 ?m or more and 0.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract: Provided are methods of forming an ion implanted region in a semiconductor device.

Abstract: A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package is disclosed. The method comprises preparing a wafer for bonding to a semiconductor package. The wafer comprises a low resistance substrate containing a RDL and a TSV for making an input/output (I/O) connection point of the semiconductor package available at another location. The RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation trench. The TSV is bounded by the isolation trench and the RDL. Preparing the wafer for bonding may comprise preparing the isolation trench that bounds the conduction path for the RDL through the low resistance substrate and bounds a vertical conduction path in a pillar for the TSV in the low resistance substrate, filling the isolation trench with isolation trench material, and preparing a wafer bonding surface.

Abstract: An insulation pattern-forming method includes forming an organic pattern on a substrate. A space defined by the organic pattern is filled with an insulating material. The organic pattern is removed to obtain an inverted pattern formed of the insulating material. The inverted pattern is cured. An insulation pattern-forming method includes forming a first organic pattern on the substrate. A space defined by the first organic pattern is filled with an insulating material. An upper surface of the first organic pattern is exposed. A second organic pattern that comes in contact with the upper surface of the first organic pattern is formed. A space defined by the second organic pattern is filled with the insulating material. The first organic pattern and the second organic pattern are removed to obtain an inverted pattern formed of the insulating material. The inverted pattern is cured.

Abstract: An organic light emitting device comprises a first substrate; a thin film transistor layer provided on the first substrate; a light emitting diode layer provided on the thin film transistor layer; and a passivation layer provided on the light emitting diode layer, the passivation layer including a first inorganic insulating film and a second inorganic insulating film, wherein a content of H contained in the first inorganic insulating film is smaller than that of H contained in the second inorganic insulating film.

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.