METHOD FOR SELECTIVELY FORMING SYMMETRICAL OR ASYMMETRICAL FEATURES USING A SYMMETRICAL PHOTOMASK DURING FABRICATION OF A SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICE
A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.
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This application is a divisional of U.S. patent application Ser. No. 11/766,931, filed on Jun. 22, 2007.
TECHNICAL FIELDVarious embodiments of the present invention relate to the field of semiconductor manufacture. More particularly, embodiments of the present invention disclose a method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask.
BACKGROUNDDuring the formation of a semiconductor device, many features such as conductive lines, contacts, dielectric isolation, and other features are commonly formed over and within a semiconductor wafer. A goal of semiconductor device engineers is to form as many of these features in a given area as possible to increase yields, decrease manufacturing costs, and to miniaturize devices. The formation of these structures typically requires the use of lithography. Optical lithography, the lithographic method most used in leading-edge wafer processing, comprises projecting coherent light of a given wavelength, typically 248 nanometers (nm) or 193 nm, from an illumination source (illuminator) through a quartz photomask or reticle having a chrome pattern representative of features to be formed, and imaging that pattern onto a wafer coated with photoresist. The light chemically alters the photoresist and enables the exposed photoresist (if positive resist is used) or the unexposed photoresist (if negative resist is used) to be rinsed away using a developer.
Semiconductor device processing often requires the formation of symmetrical features having uniform sizes, and asymmetrical features having different sizes. To form symmetrical features, a reticle having a regular chrome pattern is used to expose the photoresist. The formation of asymmetrical features, features having two (or more) different shapes and/or electrical properties, typically requires the use of two (or more) reticles, with one reticle defining the pattern of each feature.
The manufacture of reticles is time consuming and expensive due to the complexity of a typical reticle used in semiconductor device fabrication. A photolithography method which provides for the selective formation of either symmetrical features or asymmetrical features using a single reticle would be desirable.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTSThe term “wafer” is to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. Additionally, when reference is made to a “substrate assembly” in the following description, the substrate assembly may include a wafer with materials including dielectrics and conductors and features such as transistors formed thereover, depending on the particular stage of processing. In addition, the semiconductor need not be silicon-based, but may be based on silicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium, or gallium arsenide, among others. Further, in the discussion and claims herein, the term “on” used with respect to two materials, one “on” the other, means at least some contact between the materials, while “over” means the materials are in close proximity, but possibly with one or more additional intervening materials such that contact is possible but not required. Neither “on” nor “over” implies any directionality as used herein. The term “conformal” describes a coating material in which angles of the underlying material are preserved by the conformal material. The term “about” indicates that the value listed may be altered, as long as the alteration does not result in nonconformance of the process or structure in question to the illustrated embodiment of the present invention. A “spacer” indicates a material, typically dielectric, formed as a conformal material over uneven topography then anisotropically etched to remove horizontal portions of the material and leaving vertical portions of the material.
An embodiment of the present invention provides for the selective formation of either symmetrical features or asymmetrical features using a single reticle having a regular feature pattern. A process which results in the formation of a pattern of asymmetrical features is depicted by
It will be appreciated from the description below that materials other than those specified may be used for each of the materials, depending on the use of the invention. In this embodiment, the several materials depicted in
The conformal spacer material 22 of
After etching spacers 22 as depicted in
After etching the sloped recesses as depicted in
Subsequently, DARC 18, TC 16, TEOS 14, and WSix 12 are etched using a vertical anisotropic etch which is selective to spacers 22 and which stops on or in polysilicon 10 to result in the structure of
After forming the
While various continuing processes may be completed with the
In another embodiment of the invention, symmetrical features using the same reticle used to form the patterned material 20 of
After forming the structure of
Subsequently, spacers 22 may be removed selective to the exposed materials to result in the
As with the previous embodiment, the structure of
The actual structures represented by
As depicted in
The process and structure described herein can be used to manufacture a number of different structures comprising a metal material formed according to the inventive process to result in a densified metal material having decreased resistance and reduced contamination compared with conventional materials.
While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
Claims
1. A structure, comprising:
- a structure to be etched, comprising: a polysilicon material; a tungsten silicide material overlying the polysilicon material; a dielectric material overlying the tungsten silicide material; a transparent carbon (TC) material overlying the dielectric material; and an antireflective material overlying the TC material; and
- a plurality of paired cross sectional mask material spacers overlying the antireflective material.
2. The structure of claim 18, further comprising:
- the polysilicon material being about 750 angstroms (Å) and contacting the tungsten silicide material;
- the tungsten silicide material being about 900 Å and contacting the dielectric material;
- the dielectric material being a tetraethyl orthosilicate (TEOS) material about 1,400 Å and contacting the TC material;
- the transparent carbon layer being about 2,000 Å and contacting the antireflective material; and
- the antireflective material being a deposited antireflective coating (DARC) from about 200 Å to about 260 Å.
3. The structure of claim 19 further comprising:
- the plurality of paired cross sectional mask material spacers having a uniform distance between adjacent paired spacers and between adjacent pairs of spacers, wherein the distance between adjacent paired spacers is about equal to the distance between adjacent pairs of spacers;
- a plurality of first openings at a level below the plurality of paired cross sectional mask material spacers, with one first opening located between each paired spacer; and
- a plurality of second openings at a level below the plurality of paired cross sectional mask material spacers, with one second opening located between each pair of spacers,
- wherein a volume of each first opening is substantially less than a volume of each second opening.
4. A semiconductor device, comprising:
- a plurality of first features with a rectangular profile;
- a plurality of second features with an angular profile, wherein the plurality of first features are a different volume than the plurality of the second features; and
- the plurality of the first and second features are formed simultaneously.
5. The semiconductor device of claim 4, wherein the first and second features are formed simultaneously via an anisotropic etch.
Type: Application
Filed: Jun 17, 2011
Publication Date: Oct 13, 2011
Applicant: Micron Technology, Inc. (Boise, ID)
Inventors: Hongbin Zhu (Boise, ID), Jeremy Madsen (Meridian, ID)
Application Number: 13/162,889
International Classification: H01L 23/485 (20060101); H01L 29/06 (20060101);