Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: A ceramic electronic component includes an element body and at least one external electrode. The element body includes a dielectric and at least one internal electrode therein. The element body has a plurality of surfaces that includes a first surface and a second surface opposite the first surface. Two end regions are defined on the second surface at opposite ends of the second surface, and an intermediate region is defined on the second surface between the two end regions. The intermediate region has a surface roughness smaller than each of the two end regions. The respective external electrode is formed on the element body at a position away from the second surface. The respective external electrode includes a base layer formed on the element body and a plating layer formed on the base layer. The base layer is connected to the respective internal electrode and contains at least one metal.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.

Abstract: A ceramic electronic component includes an element body and at least one external electrode. The element body includes a dielectric and at least one internal electrode therein. The element body has a plurality of surfaces that includes a first surface and a second surface opposite the first surface. Two end regions are defined on the second surface at opposite ends of the second surface, and an intermediate region is defined on the second surface between the two end regions. The intermediate region has a surface roughness smaller than each of the two end regions. The respective external electrode is formed on the element body at a position away from the second surface. The respective external electrode includes a base layer formed on the element body and a plating layer formed on the base layer. The base layer is connected to the respective internal electrode and contains at least one metal.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: The invention relates to a Gunn diode comprising a first contact layer (110); a second contact layer (120); an active layer (130) based on a gallium nitride (GaN)-based semiconductor material, said active layer being formed between the first contact layer (110) and the second contact layer (120); a substrate (140) on which the active layer (130) is formed together with the first contact layer (110) and the second contact layer (120); and an optical inlet (150) for a laser (50) in order to facilitate or trigger a charge carrier transfer between extrema (210, 220) of the energy bands of the active layer (130) by means of laser irradiation.

Abstract: A coil electronic component includes a body having one surface and the other surface, opposing each other, and a plurality of wall surfaces respectively connecting the one surface and the other surface of the body, first and second recesses, respectively formed in both end surfaces of the body opposing each other among the plurality of wall surfaces of the body, extending to the one surface of the body, a wound coil, embedded in the body, including first and second lead-out portions, a first external electrode disposed along an internal wall of the first recess and the one surface of the body and connected to the first lead-out portion, and a second external electrode disposed along an internal wall of the second recess and the one surface of the body and connected to the first lead-out portion. The first and second external electrodes are spaced apart from each other.

Abstract: An electronic device includes a substrate; a porous semiconductor material layer arranged on the substrate; a first high magnetic permeability material arranged inside the pores of a first portion of the porous semiconductor layer, the first portion of the porous semiconductor material layer impregnated with the first high magnetic permeability material forming a first magnetic layer separated from the substrate by a second portion of the porous semiconductor material layer; and a coil arranged on the first magnetic layer.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.

Abstract: A substrate is provided. The substrate includes a front region having a front surface, a back region having a back surface, an edge exclusion region, and a chamfered surface. The back surface is laterally opposite the front surface. The edge exclusion region is surrounding the front region. The chamfered surface is at least partially arranged in the edge exclusion region.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: A yarn is produced having a functional core and a covering. The core is either an active functional core having electronic components or passive components and may be monofilament or multifilament. The core and covering are introduced together such that the covering protects the core and gives the core a more comfortable feel such that the yarn may be used in textile applications. The core may be covered by various spinning methods such as air jet or Vortex air jet spinning, ring spinning, open end, or friction spinning. The yarn may also be processed in a single or double covering operation. In one embodiment, the yarn is woven into clothing.

Abstract: An optical semiconductor element mounting package as well as an optical semiconductor device using the package are provided. The optical semiconductor element mounting package has a recessed part that serves as an optical semiconductor element mounting region. The package includes a resin molding and at least a pair of positive and negative lead electrodes. The resin molding is composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part. The lead electrodes are disposed opposite to each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: In a first vertical field-effect transistor in which first source regions and first connectors each of which electrically connects a first body region and a first source electrode are alternately and periodically disposed in a first direction (Y direction) in which a first trench extends, a ratio of LS [?m] to LB [?m] is at least 1/7 and at most 1/3, where LS denotes a length of one of the first source regions in the first direction, and LB denotes a length of one of the first connectors in the first direction, and LB??0.024×(VGS)2+0.633×VGS?0.721 is satisfied for a voltage VGS [V] of a specification value of a semiconductor device, the voltage VGS being applied to a first gate conductor with reference to an electric potential of the first source electrode.

Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.

Abstract: A method for making a three-dimensional semiconductor structure includes: providing a substrate, forming a first insulating layer on the substrate, and defining at least one channel hole in the first insulating layer; forming a first epitaxial layer in each channel hole and forming a second epitaxial layer stacked on the first epitaxial layer; forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, forming another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer, and forming another second epitaxial layer stacking on the another first epitaxial layer; repeating to form a plurality of sacrificial layers and a plurality of second insulating layers alternately stacked on the first insulating layer, and repeating to form a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked on the substrate.

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

Abstract: A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

Abstract: Devices for generating electrical energy along with methods of fabrication and methods of use are disclosed. An example device can comprise one or more layers of a transition metal dichalcogenide material. An example device can comprise a mechano-electric generator. Another example device can comprise a thermoelectric generator.

Abstract: Disclosed is a substrate treating apparatus. The substrate treating apparatus includes a chamber providing a space in which a substrate is treated, a support unit supporting the substrate inside the chamber, a laser unit irradiating laser to an edge region of the substrate, a vision unit capturing the edge region of the substrate to measure an offset value of the substrate, and an adjustment unit adjusting an irradiation location of the laser based on the offset value of the substrate.

Abstract: A method of manufacturing ceramic chips according to one aspect of the present disclosure includes: (A) forming a plurality of dicing trenches on a ceramic wafer; (B) removing a surface in which the dicing trenches are formed by as much as a predetermined thickness to eliminate a rough surface, which is formed on an outer side of each of the dicing trenches when the dicing trenches are formed; and (C) removing a surface opposite to the surface in which the dicing trenches are formed by as much as a predetermined thickness so that the wafer is individualized into a plurality of ceramic chips.

Abstract: A method of aligning micro light emitting elements includes supplying the plurality of micro light emitting elements on a substrate including a plurality of grooves having different shapes, the plurality of micro light emitting elements being configured to be inserted exclusively and respectively into the plurality of grooves; respectively inserting the plurality of micro light emitting elements into the plurality of grooves; and aligning the plurality of micro light emitting elements, wherein at least one groove of the plurality of grooves has a shape that is different from a shape of a respective micro light emitting element inserted into the at least one groove.

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.

Abstract: An imaging element according to the present disclosure is an imaging element flip-chip mounted on a wiring substrate, in which a projection is provided on a side surface of the imaging element such that a bottom surface side of the imaging element projects from a top surface side. Then, in the imaging device according to the present disclosure, the imaging device is flip-chip mounted on the wiring substrate so that a top surface of the imaging element faces the wiring substrate, and an outer periphery of the imaging element on the wiring substrate is sealed with a sealing material. An adhesion site of the sealing material is urged to a side of the projection, so that penetration of a solute and a solvent forming the sealing material may be reduced.

Abstract: A semiconductor structure includes a substrate, including a first region, a second region, and a third region between the first region and the second region; a first fin structure including first nanowires disposed over the first region; a second fin structure including second nanowires disposed over the second region; and a first doped layer, disposed over the third region and in contact with each first nanowire and each second nanowire. The first and second nanowires are respectively arranged along a direction perpendicular to the surface of the substrate and both contain first doping ions. The first doped layer contains second doping ions with a type opposite to the type of the first doping ions. The semiconductor structure includes a source doped layer over the first region; a drain doped layer over the second region; and a first gate structure, disposed across the first fin structure and surrounding each first nanowire.

Abstract: A light emitting element includes: a Si substrate including: a first semiconductor layer, a plurality of light emitting layers arranged in a matrix on part of an upper surface of the first semiconductor layer, and a plurality of second semiconductor layers respectively disposed on upper surfaces of the light emitting layers; a first external connection part disposed on the Si substrate at a first end of the Si substrate in a longitudinal direction; a second external connection part disposed on the Si substrate at a second end of the Si substrate opposite to the first end in the longitudinal direction; and a plurality of wiring electrodes disposed on the Si substrate, the plurality of wiring electrodes including a first wiring electrode electrically connected to the first external connection part, and a second wiring electrode electrically connected to the second external connection part.

Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.

Abstract: A photodetection element that includes: a substrate with a high infrared transmittance in a desired wavelength region; an electron barrier layer of a type-I superlattice structure, the electron barrier layer being formed above the substrate and lattice-matched to the substrate; and a light-receiving layer of a type-II superlattice structure, formed in contact with the electron barrier layer.

Abstract: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.

Abstract: The present invention relates to a method for verifying a well model, comprising the steps of receiving stored well data of an existing well, forming a model based on the received well data, submerging a tool for performing a work task into the existing well, wherein the tool is arranged to sense present well characteristics when submerged, receiving tool data corresponding to the presently sensed well characteristics from the tool, said tool data representing downhole properties relevant to downhole operation and performance of the tool, and performing a confirmation check by comparing the well data of the model with the tool data. Furthermore, the present invention relates to a well model verifying apparatus, to a well model verifying system and to a computer readable storage medium.

Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.

Abstract: Systems, computer readable medium, program code, and methods are provided for monitoring micro-electro-mechanical (“MEM”) devices removed from a wellbore by a fluid flow stream. The system can include a first MEM reader and a second MEM reader. The first MEM reader can be positionable near the fluid flow stream for detecting MEM devices entering the wellbore in a fluid flow stream. The second MEM reader can be positionable near the fluid flow stream for detecting MEM devices exiting the wellbore in the fluid flow stream. The second MEM reader can detect MEM devices exiting the wellbore in a subsequent fluid flow stream. The system can further include a computing device for determining an amount and types of MEM devices remaining in the wellbore from the first fluid flow stream and an amount and types of MEM devices removed from the well-bore by the subsequent fluid flow stream.

Abstract: A sensing device includes a shell comprising an elastomeric material, the shell including a first portion having a first end and a second portion having a second end. The shell may be egg-shaped. The first portion includes a conducting disc and a plate that includes a temperature sensor, a location sensor, and a micro-fiber composite sensor. The first portion also includes an antenna and a first electrode extending through a first hole in the first portion of the shell. The second portion includes a quantity of a metallic substance embedded on the inside surface of an end of the second portion, and a second electrode extending through a second hole in the second portion of the shell. The sensing device may be inserted into a concrete mixture, obtain measurements relating to the concrete mixture, and transmit data to a database.

Abstract: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

Abstract: A device comprises: a first plurality of fins on a semiconductor substrate, the first plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a second plurality of fins on the semiconductor substrate, the second plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a chemox layer deposited on lower portions of the fins of the first plurality of fins; and a dielectric layer deposited on the fins of the second plurality of fins. The dielectric layer is thicker than the chemox layer.

Abstract: A semiconductor structure includes a temporary substrate; a first semiconductor layer positioned on the temporary substrate; a dielectric layer comprising a plurality of patterned nano-scaled protrusions disposed on the first semiconductor layer; a dielectric layer surrounding the plurality of patterned nano-scaled protrusions and disposed on the first semiconductor layer; and a second semiconductor layer positioned on the dielectric layer, wherein the top surfaces of the patterned nano-scaled protrusions are in contact with the bottom of the second semiconductor layer. An etching process is performed on the semiconductor structure to separate the first semiconductor layer and the second semiconductor layer, in order to detach the temporary substrate from the second semiconductor layer and transfer the second semiconductor layer to a permanent substrate.

Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.

Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.

Abstract: The present invention relates to an on-chip electronic device and a method for manufacturing the same. The on-chip electronic device according to the present invention comprises a substrate, a porous layer, a plurality of magnetic bodies, and an electronic member layer. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of magnetic bodies is disposed in the plurality of voids, respectively; and the electronic member layer is disposed on one side of the porous layer, such as upper side of or lower sider of the porous layer. Because the plurality of magnetic bodies is used as the core of the inductance, the inductance is increased effectively and the area of the on-chip electronic device is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.