PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.
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1. Field
The present embodiments generally relate to the design of a memory system. More specifically, the present embodiments relate to systems, methods and circuits for communicating between a memory controller and one or more memory devices.
2. Related Art
Non-volatile flash memory has become a viable next-generation replacement for disk drives in computer systems. Such solid-state semiconductor memory has a number of advantages relative to the rotating magnetic storage used in disk drives, including reliability, faster access times and lower power consumption. In contemporary non-volatile memory architectures that require large capacity, each memory device communicates with a memory controller through a large number of communication links which carry command, address, and data information. However, providing such a large number of links with high bandwidth to a large number of non-volatile memory devices results in a memory system which is complicated, expensive and incompatible with, for example, modern Flash memory core and interface attributes.
The disclosed embodiments demonstrate a relatively simple and low-cost system for communicating between a memory controller and a large number of solid-state semiconductor memory devices. A protocol in an embodiment which facilitates high bandwidth data transfers to a large number of devices begins with a request for the memory access from a memory controller to a memory device. The system then performs a timing-calibration operation for a data transfer between the memory controller and the memory device before performing the data transfer.
More specifically, referring to the flow chart illustrated in
In response to this access request, one or more power sources on the memory device are enabled. These power sources are associated with a faster, point-to-point data link with a low-swing voltage (step 104). Next, the system/memory device/controller performs a calibration operation for the data link (step 106). This calibration operation can involve: (1) calibrating a phase relationship between a timing reference and a data signal on the data link; and/or (2) locking a “locked loop,” which provides a timing reference for communications on the data link. This locked loop can include any one of a number of loop circuits which are used to provide a timing reference, such as a phase-locked loop (PLL) or a delay-locked loop (DLL).
After the data link is initialized and calibrated, data associated with the access request is transmitted across the data link (step 108). For example, for a read operation, the data is transported from the memory device to the memory controller, whereas for a write operation the data is transported from the memory controller to the memory device.
Finally, after the requested memory access is complete, the one or more power sources which were enabled in step 104 are disabled in step 110. In implementations which, for example, desire low power consumption, it is advantageous to disable the one or more power sources associated with the data link because the data link only services a single memory device and the memory device may not be accessed again for a long period of time, while other memory devices (which are associated with other data links) are being accessed.
Voltage-Swing Differentiated Command/Data InterfaceA block diagram for an embodiment of a system using voltage swing differentiated command/data transfer appears in
The DQ circuitry additionally includes a number of 8:1 serializers which prepare the data for transmission over the serial DQ link by multiplexing a parallel set of 8 data bits to a single bit serial data stream for output by a transmitter. Data output from the transmitter is launched synchronously with respect to rising and falling edges of a clock signal such that two bits are transmitted per clock cycle for each single bit serial stream. In addition, the DQ circuitry includes a number of corresponding 1:8 de-serializers, which convert incoming single bit wide serial data from the DQ link into 8-bit parallel data. The serialization ratio of 8-to-1 in these circuits is merely exemplary. Hence, other embodiments can use other serialization ratios, such as 4-to-1 or 16-to-1.
The DQ circuitry also includes circuitry which uses phase-adjustment values to calibrate the timing for the communications across the ˜3.2 Gb/s link, as well as comparators which are used during the calibration process. This calibration process can involve “shmooing” or any other existing or future technique for calibrating the timing of data relative to a timing reference signal during a memory operation. For example, in some embodiments, this calibration involves adjusting a sampling clock on a receiver to sample a center of a data eye of the data signal, or alternatively, phase-shifting the launch of the data at the transmitter such that the data is sampled at the receiver in the middle of the data eye. After the received data is sampled with a phase-adjusted clock signal, the comparators are used to compare sampled data with the original test pattern to determine the boundaries of the data eye. The above-described operations can take place with transmitters and/or receivers located at either the memory controller or the memory device.
Moreover, the timing-calibration operation can involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time, wherein a tBIT time is the period of time that defines a valid single bit of data and a transmit tBIT time is the time required for a transmitter circuit to transmit a single bit of data onto an external signal line. Hence, the phase-adjustment for the timing calibration operation can possibly be larger than a transmit bit time, which means that the calibration technique needs to account for the fact that the phase-adjustment may need to be larger than one tBIT time.
The interface circuitry also includes a transmitter on memory controller 202 and a receiver on flash memory device 204 for the ˜0.4 GHz reference clock signal, which is transmitted from memory controller 202 to flash memory device 204.
The interface circuitry additionally includes transmitters and receivers for a low-performance, large-swing CA link between memory controller 202 and flash memory device 204. The CA circuitry in memory controller 202 includes a separate phase-adjustment value for each flash memory device, which enables the CA link to provide a different calibration for each individual flash memory device.
After the PLLs are locked, memory controller 202 sends a two-byte command to perform a phase-adjustment operation to flash memory device 204. For example, this phase-adjustment operation can involve sending one or more test data patterns from flash memory device 204 to memory controller 202 across the DQ link. In general, this phase-adjustment operation involves calibrating a phase relationship between a timing reference and an associated data signal. Moreover, this phase-adjustment operation can take place at any time during the 25 μs which is required to access the read data in flash memory device 204. Additionally, the phase-adjustment operation can involve a calibration in which an adjustable transmit or receive phase is created by adjusting a phase-interpolator structure. This allows one of a set of clock signals (typically four to eight) which are evenly spaced across the 360 degrees of one clock cycle to be selected to provide a coarse phase adjustment, and an interpolated phase value to be created from a pair of these adjacent clock phases to provide a fine phase adjustment.
After the phase-adjustment operation is complete and the read data is retrieved from within flash memory device, memory controller 202 sends a two-byte data-transfer command across the CA link, and a 4096-byte block data transfer subsequently takes place from memory device 204 to memory controller 202 across the DQ link, which requires about 10 μs.
Finally, at the end of this block data transfer, memory controller 202 sends a two-byte sleep command across the CA link, which causes the power sources associated with the DQ link to be disabled.
Although six-bytes is a useful exemplary size for a write command (assuming typical encoding and addressing requirements for memory operations), the disclosed embodiments are not meant to be limited to commands, addresses or data transfers that have specific sizes. The optimal sizes for these items will vary between systems based on various system parameters, such as the ratio between the access time to the memory core and the available interface bandwidth.
Next, the system takes about 0.3 μs to lock one or more PLLs located on memory controller 202 and/or flash memory device 204. At the same time, the system can enable one or more power sources associated with the high-speed DQ link (not shown in
After the PLLs are locked, memory controller 202 sends a two-byte command to perform a phase-adjustment operation to flash memory device 204. This phase-adjustment operation involves sending one or more data patterns from flash memory device 204 to memory controller 202 across the DQ link.
After the phase-adjustment operation is complete, memory controller 202 sends a two-byte data transfer command across the CA link, and a 4096-byte block data transfer subsequently takes place from the memory controller to the flash memory device across the DQ link, which requires about 10 μs. Two bytes (16 bits) is estimated to be the shortest practical command length for simple operations, such as scheduling a data transfer or placing a device into a specific power state. The 16 bits can contain an opcode and a device address (remember that the CA link is shared by a number of memory devices). The 10-12 bytes of information required for a complete transaction takes only about 100 ns of time to be transferred across the shared CA link, meaning that dozens of memory devices could potentially be controlled though the single, shared CA link.
Next, it takes about 300 μs to write the data internally within the flash memory device, during which time the DQ link and the CA link are not performing any operations related to the write transaction.
Finally, after the data is written internally within the flash memory device, memory controller 202 sends a two-byte sleep command across the CA link, which causes the power sources associated with the DQ link to be disabled. The power sources which are disabled can include, but are not limited to, power sources for: (1) a phase-locked loop (PLL) or a delay-locked loop (DLL); (2) a transmitter for the data link; (3) equalization circuitry associated with the data link; (4) a digital-to-analog (D/A) converter associated with communications across the data link; (5) an analog-to-digital (A/D) converter associated with communications across the second link; (6) a differential pair which comprises a communication channel for the data link; and (7) clocking circuitry in a clock tree for the memory device. In one embodiment, a sleep command is directed to an individual memory component on the CA link, and instructs the memory component to transition from an active transfer power state to a sleep state, in which DC current sources are shut off, clock trees are disabled, and the only power dissipated by the device is junction leakage. In this sleep state, a small amount of CMOS logic will be listening to the CA link, and when a six-byte read or write command is directed to the device, the CMOS logic will wake up and start the access and associated calibration processes.
Alternatively, the control register read operation could be carried out at the same bit rate as the control register write operation (1.25 ns per bit instead of 5.0 ns as shown). This would require calibrating the receiver in the controller so it correctly samples in the middle of each bit time, compensating for the round trip of the clock to the memory device and the read data back to the controller. By running slower, as shown, the calibration could be avoided (this depends upon the length of the multi-drop bus). A single receiver design could accommodate both signaling rates.
Asymmetric Interface with Bit-Rate Clock Signal
Alternatively, instead of sending a 1.6 GHz bit rate clock CKD, a second half bit rate clock running at 0.8 GHz could be sent. This second CKD clock would be shifted 90 degrees with respect to the 0.8 GHz CKC (this is also known as a “quadrature relationship”). CKD can also be a large swing signal, like CKC. The two clocks provide enough timing events to transmit and receive bits on the DQ link at the full 3.2 GHb/s rate. It is also easier to distribute the two slower clocks on the bus and inside the memory device. The transmit and receive phase adjustment values used in the controller for a particular DQ[i] link could include an offset phase between adjacent bits to account for skew between the two clock signals. For example, if the CKC and CKD signals had edges at 0, and 180 degrees and 70 and 250 degrees (20 degrees of skew) at memory device[i], then the sampling times would include the skew for alternate bits: 1, 70, 180, 250, 1, 70, 180, 250, 1, 70, 180, 250, etc.
The DQ circuitry at memory controller 802 also includes phase-adjustment values to calibrate the timing for communications across the ˜3.2 Gb/s link, as well as comparators which are used during the calibration process. In this embodiment, the DQ circuitry on flash memory device 804 does not include such comparators or phase-adjustment values, since the timing calibration operations for transmit timing adjustment and receive timing adjustment are performed on the controller. Instead, the DQ circuitry on flash memory device 804 includes storage for test patterns, which is used during the calibration process.
Alternatively, logic for performing pattern-generation and pattern-checking could be used instead of the pattern storage element shown in
The interface circuitry also includes a transmitter on memory controller 802 and a receiver on flash memory device 804 for the ˜0.4 GHz reference clock signal which is transmitted from memory controller 802 to flash memory device 804.
The interface circuitry additionally includes transmitters and receivers for the low-performance, large-swing CA link between memory controller 802 and flash memory device 804. This CA circuitry on memory controller 802 provides a separate phase-adjustment value for each flash memory device, which enables the CA link to have a different calibration for each flash memory device.
As mentioned previously, this low-swing clock signal provides a timing reference for communications across the low-swing DQ link. Hence, it is unnecessary for this low-swing clock signal to be active when memory transactions are not taking place. However, this low-swing clock signal 808 can remain active to serve as a timing reference for other memory transactions associated with other flash memory devices.
Each DQ link is additionally coupled to transmitters and receivers for the low-performance, large-swing CA signals between memory controller 1402 and flash memory device 1404. This CA circuitry in memory controller 1402 includes a separate phase-adjustment value for each flash memory device, which enables the CA link to provide a different calibration for each individual flash memory device.
Both the high-speed, low-swing transmitters and receivers and the low-speed, large swing transmitters and receivers are coupled to the same bidirectional DQ links 1502.
This interface circuitry also includes a transmitter on memory controller 1402 and a receiver on flash memory device 1404 for the ˜0.4 GHz reference clock signal which is transmitted from memory controller 1402 to flash memory device 1404.
The preceding description was presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present embodiments.
Moreover, embodiments of one or more of these circuits, integrated circuits, devices, systems and/or techniques may be used in memory systems and/or memory devices that include different types of memory, such as: volatile memory, non-volatile memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), NAND or NOR Flash, a fully buffered NAND Flash memory module, solid-state memory, resistance-change memory (such as RRAM), phase-change memory (PCM), and/or another type of memory. Moreover, for a given type of memory, these techniques may be used in different memory technologies or technology generations (which may use different power supply voltages).
Additionally, the systems described above can be implemented as a non-volatile memory solution for a solid-state disk system. Such a system can be used as a drop-in replacement for hard disk drives to store files, or other types of secondary store devices.
Hence, embodiments of one or more of these circuits can be used to provide random-access memory or non-volatile secondary storage in a computing device, which can generally include any type of computing device, including, but not limited to, a computer system based on a microprocessor, a mainframe computer, a digital signal processor, a portable computing device, a personal organizer, a cell phone, a device controller, or a computational engine within an appliance.
The term “flash memory” as used in this disclosure is intended to refer any one of a number of exemplary technologies from a large set of high-capacity memory technologies. This set is characterized by large block transfers because of the need to reduce the access time overhead, which results in a large imbalance in the DQ/RQ information per transaction. Many of these high-capacity memory technologies are non-volatile.
The foregoing descriptions of embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present description to the forms disclosed. Thus, the present embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present description. The scope of the present description is defined by the appended claims.
Claims
1. A method for controlling an integrated circuit memory device by a memory controller, the method comprising:
- sending a memory-access request to the memory device;
- after sending the memory-access request, sending to the memory device a command that specifies performing a timing-calibration operation for a data transfer associated with the memory-access request; and
- performing the data transfer for the memory-access request;
- wherein the timing-calibration operation occurs between sending the memory-access request and the data transfer associated with the memory-access request.
2. The method of claim 1, wherein the memory device is a non-volatile semiconductor memory.
3. The method of claim 2, wherein the memory device is a flash memory.
4. The method of claim 1, wherein the memory-access request is a write command, and wherein the method further comprises enabling a current source of an input receiver disposed on the memory device such that transferring the data includes receiving the data by the input receiver, and wherein the enabling of the current source and the receiving of the data are triggered at the memory device in response to the write command.
5. The method of claim 1, wherein the memory-access request is a read command, and wherein the method further comprises enabling a current source of a transmitter disposed on the memory device such that transferring the data includes transmitting the data using the transmitter, and wherein the enabling of the current source and the transmitting of the data are triggered at the memory device in response to the read command.
6. The method of claim 1,
- wherein the memory-access request is sent through a first link between the memory controller and the memory device; and
- wherein the data transfer takes place through a second link between the memory controller and the memory device.
7. The method of claim 6, wherein the second link operates at a higher frequency than the first link.
8. The method of claim 7, wherein communications across the second link have a lower voltage swing than communications across the first link.
9. The method of claim 6,
- wherein sending the memory-access request to the memory device through the first link involves sending the memory-access request through a multi-drop link which couples the memory controller to multiple memory devices; and
- wherein performing the data transfer through the second link involves sending the data though a point-to-point link which couples the memory controller to a single memory device.
10. The method of claim 6,
- wherein sending the memory-access request to the memory device through the first link involves sending the memory-access request through a single-ended link; and
- wherein performing the data transfer through the second link involves sending the data though a differential link.
11. The method of claim 6, wherein the first link and the second link share a common communication channel.
12. The method of claim 1, wherein the timing-calibration operation involves:
- locking a locked loop which provides a timing reference for communications on the second link; and/or
- calibrating a phase relationship between a clock signal generated based on the timing reference and a data signal on the second link.
13. The method of claim 1, wherein performing the timing-calibration operation involves:
- performing phase adjustments at the memory controller without associated phase adjustments at the memory device;
- performing phase adjustments at the memory device without associated phase adjustments at the memory controller; or
- performing phase adjustments at both the memory controller and the memory device.
14. The method of claim 1, wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time.
15. The method of claim 14, wherein the timing-calibration operation involves:
- setting a phase offset for the timing calibration to a minimum possible value; and
- sweeping through an entire phase range and noting a fail-pass point and a pass-fail point for a data link between the memory controller and the memory device;
- wherein the entire phase range includes multiple tBIT times.
16. The method of claim 1, wherein the timing-calibration operation additionally involves enabling power sources for one or more of the following:
- a PLL;
- a DLL;
- a transmitter associated with the second link;
- equalization circuitry associated with the second link;
- a digital-to-analog converter associated with communications across the second link;
- an analog-to-digital converter associated with communications across the second link;
- a differential pair which comprises a communication channel for the second link; and
- clocking circuitry in a clock tree for the memory device.
17. The method of claim 1, wherein the method further comprises providing a bit-rate clock signal on a multi-drop link from the memory controller to multiple memory devices, wherein the bit-rate clock signal provides a frequency/phase reference for the second link.
18. A memory system, comprising:
- a memory controller;
- a memory device;
- a first link to communicate memory-access requests from the memory controller to the memory device; and
- a second link to communicate data associated with memory-access requests between the memory controller and the memory device;
- wherein after a memory-access request is communicated, the memory system is to perform a timing-calibration operation for the second link, and transfer data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between communicating the memory-access request and transferring the data associated with the memory-access request.
19. The memory system of claim 18, wherein the memory device is a non-volatile semiconductor memory.
20. The memory system of claim 19, wherein the memory device is a flash memory.
21. The memory system of claim 18, wherein when the memory-access request is a write command, the memory device is to enable a current source of an input receiver disposed on the memory device such that transferring the data includes receiving the data by the input receiver, and wherein enabling the current source and receiving the data are triggered at the memory device in response to the write command.
22. The method of claim 18, wherein when the memory-access request is a read command, the memory device is to enable a current source of a transmitter disposed on the memory device such that transferring the data includes transmitting the data using the transmitter, and wherein the enabling of the current source and the transmitting of the data are triggered at the memory device in response to the read command.
23. The memory system of claim 18, wherein the second link operates at a higher frequency than the first link.
24. The memory system of claim 23, wherein communications across the second link have a lower voltage swing than communications across the first link.
25. The memory system of claim 18,
- wherein the first link is a multi-drop link which couples the memory controller to multiple memory devices; and
- wherein the second link is a point-to-point link which couples the memory controller to a single memory device.
26. The memory system of claim 18,
- wherein the first link is a single-ended link; and
- wherein the second link is a differential link.
27. The memory system of claim 18, wherein while performing the timing-calibration operation, the memory system is to:
- lock a locked loop which provides a timing reference for communications on the second link; and/or
- calibrate a phase relationship between a clock signal generated based on a timing reference and a data signal on the second link.
28. The method of claim 18, wherein while performing the timing-calibration operation, the memory system is to:
- perform phase adjustments at the memory controller without associated phase adjustments at the memory device;
- perform phase adjustments at the memory device without associated phase adjustments at the memory controller; or
- perform phase adjustments at both the memory controller and the memory device.
29. The memory system of claim 18, wherein while calibrating the phase relationship, the memory system is to perform multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time.
30. The method of claim 29, wherein while calibrating the phase relationship, the memory system is to:
- set a phase offset for the timing calibration to a minimum possible value; and
- sweep through an entire phase range and to determine a fail-pass point and a pass-fail point for a data link between the memory controller and the memory device;
- wherein the entire phase range includes multiple tBIT times.
31. The memory system of claim 18, further comprising power-source enablement circuitry, wherein in response to a memory-access request, the power-source enablement circuitry is to enable a power source for one or more of the following:
- a PLL;
- a DLL;
- a transmitter associated with the second link;
- equalization circuitry associated with the second link;
- a digital-to-analog converter associated with communications across the second link;
- an analog-to-digital converter associated with communications across the second link;
- a differential pair which comprises a communication channel for the second link; and
- clocking circuitry in a clock tree for the memory device.
32. The memory system of claim 18, further comprising a multi-drop link which provides a bit-rate clock signal from the memory controller to multiple memory devices, wherein the bit-rate clock signal provides a frequency/phase reference for the second link, thereby eliminating the need for a PLL or a DLL on the memory device.
33. The memory system of claim 18, wherein the first link and the second link share a common communication channel.
34. A memory controller, comprising:
- a first interface to communicate memory-access requests to a memory device;
- a second interface to communicate data associated with the memory-access requests between the memory controller and the memory device;
- wherein after sending a memory-access request, the memory controller is to: send to the memory device a command that specifies performing a timing-calibration operation through the first interface, and transfer data associated with the memory-access request through the second interface, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.
35. The memory controller of claim 34, further comprising a bit-rate clock interface for a multi-drop link which provides a bit-rate clock signal from the memory controller to multiple memory devices, wherein the bit-rate clock signal provides a frequency/phase reference for the second interface, thereby eliminating the need for a PLL or a DLL on the memory device.
36. The memory system of claim 34, wherein the first interface and the second interface share a common communication channel between the memory controller and the memory device.
37. The memory system of claim 34, wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time.
38. A memory, comprising:
- a first interface to receive memory-access requests from a memory controller; and
- a second interface to communicate data associated with memory-access requests between the memory and the memory controller;
- wherein in response to a memory-access request of the memory-access requests, the memory is to perform a timing-calibration operation for the second interface, wherein the timing-calibration operation is executed during a time interval that transpires between receiving the memory-access request and communicating the data associated with the memory-access request.
39. The memory of claim 38, further comprising a bit-rate clock input to receive a bit-rate clock signal from the memory controller, wherein the bit-rate clock signal provides a frequency/phase reference for the second interface, thereby eliminating the need for a PLL or a DLL at the memory device.
40. The memory of claim 38, wherein the first interface and the second interface share a common communication channel between the memory controller and the memory device.
41. The memory of claim 38, wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time.
42. A memory system, comprising:
- a memory controller;
- a memory device;
- a first link to communicate memory-access requests from the memory controller to the memory device;
- a second link to communicate data associated with memory-access requests between the memory controller and the memory device;
- wherein the first link and the second link share a common communication channel;
- wherein after a memory-access request is communicated, the memory system is to perform a timing-calibration operation for the second link, and transfer data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between communicating the memory-access request and transferring the data associated with the memory-access request.
43. The memory system of claim 42, wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time.
Type: Application
Filed: Jan 5, 2010
Publication Date: Oct 27, 2011
Applicant: RAMBUS INC. (Los Altos, CA)
Inventors: Frederick A. Ware (Los Altos Hills, CA), Holden Jessup (Palo Alto, CA)
Application Number: 13/143,760
International Classification: G06F 12/00 (20060101); G06F 12/02 (20060101);