Abstract: A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.

Abstract: An approach allows concurrent execution of near-memory processing commands, referred to herein as “PIM commands,” and host memory commands. A memory controller determines and issues a plurality of register-only PIM commands that do not reference memory with host memory commands to allow concurrent execution of the register-only PIM commands and the host memory commands. The approach allows concurrent execution of register-only PIM commands and host memory commands without interference, even when the register-only PIM commands and the host memory commands are interleaved, and even for the same memory module, which improves resource utilization and performance. Further improvement of resource utilization and performance is achieved by extending a register-only phase by reordering register-only PIM commands before non-register-only PIM commands, subject to dependency constraints, and using shadow row buffers to provide local working copies of data from memory to near-memory compute elements.

Abstract: An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

Abstract: Methods, systems, and devices for alignment of activation periods are described. Techniques for memory operations are described. A device may transition from a reduced-power state to a reception-ready state based on a timing parameter of the device that indicates a first duration for transitioning the device from the reduced-power state to the reception-ready state. After transitioning to the reception-ready state, a data transmission may be received beginning at a first time. A second time associated with an error in the data transmission may be determined. The timing parameter may be configured to indicate a second duration for transitioning the device to the reception-ready state based on a difference between the second time and the first time.

Abstract: Embodiments of the present disclosure relate to a memory system and operation method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks, wherein each of the plurality of memory blocks include a plurality of pages; and ii) a memory controller configured to determine a first super memory block among a plurality of super memory blocks, wherein each of the plurality of super memory blocks includes one or more of the plurality of memory blocks, set a lock to prevent a background operation from being executed for the first super memory block, and transmit data stored in the first super memory block to an external device.

Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.

Abstract: A method, computer program product, and computer system for generating and using a basic state layer. N task models are provided (N?2). Each task model was trained on a same pre-trained backbone model. Each task model includes M feature layers and a task layer (M?1). Each feature layer of each task model includes a parameter matrix that is different for the different models. An encoder-decoder model is trained. The encoder-decoder model includes sequentially: an input layer, an encoder, M hidden layers, a decoder, and an output layer. The encoder is a neural network that maps and compresses the parameter matrices in the input layer into the M hidden layers, which generates a basic state model. The decoder is a neural network that receives the basic state model as input and generates the output layer to be identical to the input layer.

Abstract: The invention relates to a method and an apparatus for programming data into flash memory. The method includes: obtaining, by the accelerator, an execution table indicating that data related to the first virtual carrier need to go through a mid-end and a back-end processing stages earlier than data related to other virtual carriers; driving, by the routing engine, a host interface (I/F) to obtain data associated with all cargos in the second virtual carrier, updating the second cargo flags with third cargo flags to indicate that data associated with all the cargos in the second virtual carrier are prepared in the front-end processing stage; and determining, by the accelerator, that data associated with any cargo in the first virtual carrier hasn't been prepared according to information of the first cargo flags, and disallowing the second virtual carrier to proceed to the following processing stages.

Abstract: Apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. One example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. The algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.

Abstract: A storage device may include a storage comprising a plurality of dies each having a plurality of memory blocks, and configured to provide a default ZNS (Zoned NameSpace) size to a host device; and a controller configured to generate a ZNS by selecting one or more memory blocks corresponding to a required ZNS size from the plurality of dies to allocate the selected memory blocks to the ZNS in response to a ZNS generation request signal which includes the required ZNS size and is provided from the host device.

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

Abstract: A system includes a memory including a ring buffer having a plurality of slots, a processor in communication with the memory, a guest operating system, and a hypervisor. The hypervisor is configured to detect a request associated with a memory entry, retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot, and test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged. Additionally, the hypervisor is configured to execute the request associated with the memory entries and respective valid descriptors. The hypervisor is also configured to walk the ring buffer backwards from the end slot to the original slot while clearing the valid descriptors.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A memory control method is disclosed according to an embodiment. The method includes: temporarily storing first type data into a buffer memory, wherein the first type data is preset to be stored into a rewritable non-volatile memory module based on a first programming mode; in a state that the first type data is stored in the buffer memory, temporarily storing second type data into the buffer memory, and the second type data is preset to be stored into the rewritable non-volatile memory module based on a second programming mode different from the first programming mode; and in a state that a data volume of the first type data in the buffer memory does not reach a first threshold, if a data volume of the second type data in the buffer memory reaches a second threshold, storing the first type data in the buffer memory into the rewritable non-volatile memory module.

Abstract: The disclosed technology provides techniques, systems, and apparatus for containing and recovering from uncorrectable memory errors in distributed computing environment through migration of virtual machines and associated memory to a target host machine. An aspect of the disclosed technology includes a hypervisor or virtual machine manager that receives signaling of an uncorrectable memory error detected by a host machine. The virtual machine manager then uses information received via the signaling to identify virtual memory addresses or memory pages associated with the corrupted memory element so as to allow for containment and recovery from the error, and for live migration of the virtual machine.

Abstract: A technique efficiently migrates a live virtual disk (vdisk) across storage containers of a cluster having a plurality of nodes deployed in a virtualization environment. Each node is embodied as a physical computer with hardware resources, such as processor, memory, network and storage resources, that are virtualized to provide support for one or more user virtual machines (UVM) executing on the node. The storage resources include storage devices embodied as a storage pool that is logically segmented into the storage containers configured to store one or more vdisks. The storage containers include a source container having associated storage policies and a destination container having different (new) storage policies.

Abstract: A system update appliance includes a processor and a memory device with a Content Addressable Storage (CAS) space and a location addressable storage space. The location addressable storage space partitioned into an object storage space and a device storage space. The processor stores a device entry in the device storage space. The device entry is associated with a device external to the system update appliance and includes a component entry for a component of the device. The component operates based on an update. The component entry includes a description of the component and a pointer to a record stored in the CAS space. The processor stores the record in the CAS space. The record is associated with a combination of the component and the first update. The record includes the description, a second pointer to an update repository, and a third pointer to the object storage space.

Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.

Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including detecting a failure of a key-value store, identifying a non-filled zone of the memory device resulting from the failure, wherein the non-filled zone stores, in the key-value store, at least one of: an uncommitted key block or an uncommitted value block, and recovering the non-filled zone to obtain a recovered zone.

Abstract: A memory device, a host device and a memory system are provided. The memory device may include a plurality of storage units configured to store data, and at least one device controller configured to, receive a read command from at least one host device and to read data stored in the plurality of storage units in response to the read command, the at least one host device including at least one host memory including a plurality of HPB (high performance boosting) entry storage regions, and provide the at least one host device with a response command, the response command indicating an activation or deactivation of the plurality of HPB entry storage regions, the response command including HPB entry type information which indicates a HPB entry type of the HPB entry storage region.

Abstract: Embodiments are directed to tiered data store with persistent layers. A write tier in the file system for storing in a file system. A value for a performance metric that corresponds to write requests to the file system may be predicted based on characteristics of the write requests such that the performance metric may be determined based on a plurality of interactions with the write tier. The predicted value that exceeds a threshold value of the performance metric may be employed to cause performance of further actions, including: queuing a portion of the write requests in a memory buffer based on the predicted value and the threshold value; combining the queued portion of the write requests into s; storing the data segments in the write tier such that a measured value of the performance metric may be less than the threshold value.

Abstract: Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

Abstract: Various embodiments of the present disclosure provide a method for prediction of device failure. The method includes receiving from a network exposure node a request for subscribing to a monitoring report related to a device failure predicted for a terminal device; obtaining, in response to the request, traffic data and current power consumption data of the terminal device; detecting, based on the traffic data, a traffic anomaly of the terminal device; predicting, in response to the detection of the traffic anomaly of the terminal device, a device failure based on the current power consumption data; and transmitting the monitoring report indicating the predicted device failure to the network exposure node. According to the embodiments of the present disclosure, the monitoring event can be extended to predict the device failure of the terminal device.

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.

Abstract: Embodiments of a system for determining a data gravity index score and implementing pervasive data center architecture is disclosed. In some embodiments, the system can calculate a data gravity index score based on the amount of data stored in a given location, an amount of data in motion in the given location, a bandwidth index associated with the given location, and a latency index associated with the given location. Based on data gravity index scores, in some embodiments, the system can localize traffic to improve network performance, improve security operations, and generate software-defined-network overlay.

Abstract: A storage device includes a plurality of nonvolatile memories, each including a plurality of memory blocks and a controller configured to control the plurality of nonvolatile memories, in which the controller is configured to buffer data chunks received along with write commands from a host, is configured to determine a size of continuous data based on a start logical address and a chunk size of the data chunks, is configured to determine a striping number indicating a number of nonvolatile memory which is for distributing and storing the data chunks in sub-page units based on the size of continuous data, and is configured to provide the data chunks to one or more nonvolatile memories selected from among the plurality of nonvolatile memories based on the determined striping number and the one or more selected nonvolatile memories are configured to perform a programming operation on the data chunks in parallel.

Abstract: A method for contention reduced update of one or more storage system parameters, the method may include (i) concurrently monitoring the one or more storage system parameters (SSPs) by compute entities (CEs); wherein the concurrently monitoring comprises updating, by the CEs, local counters allocated to different SSPs; (ii) updating, by the CEs, sets of shared counter fields with values of the local counters, wherein different sets are allocated to different SSPs; wherein an updating of a set of a shared counter fields by an CE comprises selecting a shared counter field of the set by the CE; and (iii) calculating values of the different SSPs, wherein a calculating of a value of a SSP is based on at least one value of at least one shared counter field of a set that is allocated to the SSP.

Abstract: A virtual network comprising virtual machines executing at a computing environment remote from the virtualized computing service provider is implemented. A control plane management functions is configured to provide and implement the virtual machines of the virtual network and executed at the virtualized computing service provider. Data plane management functions are configured to manage data traffic to and from the virtual machines of the virtual network and executed at the remote computing environment. A secure network connection between the virtualized computing service provider and the remote computing environment is established. The control plane management functions cause instantiation of the virtual machines of the virtual network at the remote computing environment. Using the control plane management functions executing at the virtualized computing service provider, operation of the virtual machines of the virtual network is managed.

Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

Abstract: A memory sub-system to, in response to a power up, executing a first loading process to load a sequence of a set of trim values into one or more registers of the memory sub-system. In response to a request to execute a memory access operation, interrupting the first loading process. A second loading process including loading a portion of the set of trim values corresponding to the request is executed. The memory access operation is executed using the portion of the set of trim values loaded into the one or more registers during the second loading process. Following execution of the memory access operation, the first loading process is resumed to load one or more unloaded trim values of the sequence of trim values.

Abstract: An apparatus comprises a processing device configured to identify storage workloads to be run on a storage system, and to determine a mix of input/output (TO) patterns associated with the identified storage workloads, the mix of IO patterns comprising a first set of IO patterns characterizing types of IO operations performed by a first storage workload and at least a second set of IO patterns characterizing types of IO operations performed by a second storage workload. The processing device is also configured to calculate an affinity metric for the mix of IO patterns, the calculated affinity metric characterizing a difference between (i) performance metrics for the mix of IO patterns running concurrently and (ii) the first and second sets of IO patterns running individually. The processing device is further configured to allocate the identified storage workloads to storage devices of the storage system based on the calculated affinity metric.

Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.

Abstract: An information handling system includes a memory module, a memory controller coupled to the memory controller by a memory bus, and an expansion memory device coupled to the memory controller by a data communication interface. The memory controller receives user data, calculates error correction code (ECC) data for the user data, determines metadata related to the user data, writes the user data and the ECC data to the memory module via the memory bus, and stores the metadata to the expansion memory device with a transaction on the data communication interface.

Abstract: A computing system with a data store including storage priorities each associated with a different predefined event type. The storage priority indicating a likelihood detection of the predefined event type by an autonomous vehicle causes the autonomous vehicle to store sensor system output from a sensor system in the autonomous vehicle. The computing system can receive a data storage request indicating a request for the autonomous vehicle to store sensor system output for a specific predefined event type. The computing system can further update the storage priorities. Updating the storage priorities includes updates a storage priority associated with the specific predefined event type based on a parameter of specific predefined event type. The computing yet further can transmit the updated storage priorities to the autonomous vehicle which causes the autonomous vehicle to change the amount of sensory system output stored by the autonomous vehicle.

Abstract: A memory controller includes a first buffer configured to receive a first memory request from a host and store the first memory request, a request scheduler configured to determine an order in which the first memory request is transferred to a command generator, a request generator configured to generate one or more second memory requests based on a generation parameter of the first memory request, in response to an address of the first memory request corresponding to a processing in memory (PIM) memory, the command generator configured to generate a first command corresponding to the first memory request and one or more second commands corresponding to the one or more second memory requests, and store the generated first command and the one or more second commands in a second buffer, and a command scheduler configured to schedule the first command and the one or more second commands.

Abstract: Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.

Abstract: A memory device can include a plurality of memory cells for storing data, a memory interface configured to store and retrieve data at the plurality of memory cells, a logic unit comprising digital circuitry configured to perform mathematic and logic operations, and a control circuitry configured to control operation of the memory device.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

Abstract: A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.

Abstract: A controller is provided. The controller includes a write queue configured to store commands for operating a memory device that are generated based on requests received from a host, zone identifications of the commands each indicating a memory region in the memory device to store data corresponding to a command, and write pointers of the commands each indicating an order that the requests are output from the host; and a queue controller configured to receive the commands, the zone identifications, and the write pointers from the write queue, store the commands in buffers allocated the zone identifications based on the write pointers, respectively, and based on an occurrence of an event that a number of commands stored in a buffer among the buffers reaches a preset number set in the buffer, output commands stored in the buffer.

Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.

Abstract: An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses. The counters are configured to count activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; For example, in response to an activation command applied to a row address having first sub-addresses, counts stored in a portion of the counters corresponding to the first sub-addresses are increased for the count of the activation command. For each respective segment, counts stored in counters for sub-addresses in the respective segment are used to determine whether at least one of the sub-addresses has seen more activation commands than a threshold. An alert is generated for risk mitigation operations in response to each segment having at least one sub-address that has seen more activation commands than the threshold.

Abstract: The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.

Abstract: Disclosed are devices, systems and methods for polar coding and decoding for correcting deletion and insertion errors caused by a communication channel. One exemplary method for error correction includes receiving a portion of a block of polar-coded symbols that includes d?2 insertion or deletion symbol errors, the block comprising N symbols, the received portion of the block comprising M symbols; estimating, based on one or more recursive calculations in a successive cancellation decoder (SCD), a location or a value corresponding to each of the d errors; and decoding, based on estimated locations or values, the portion of the block of polar-coded symbols to generate an estimate of information bits that correspond to the block of polar-coded symbols, wherein the SCD comprises at least log2(N)+1 layers, each comprising up to d2N processing nodes arranged as N groups, each of the N groups comprising up to d2 processing nodes.

Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

Abstract: The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.

Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.