FIELD EFFECT TRANSISTOR WITH TRENCH FILLED WITH INSULATING MATERIAL AND STRIPS OF SEMI-INSULATING MATERIAL ALONG TRENCH SIDEWALLS
In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region.
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This application is a division of U.S. application Ser. No. 11/862,396, filed Sep. 27, 2007, which is a division of U.S. application Ser. No. 10/931,887, filed Aug. 31, 2004, which is a division of U.S. application Ser. No. 10/200,056, filed Jul. 18, 2002. The disclosures of U.S. application Ser. Nos. 10/200,056 and 11/862,396 are incorporated herein by reference for all purposes.
BACKGROUND OF THE INVENTIONPower field effect transistors, e.g., MOSFETs (metal oxide semiconductor field effect transistors), are well known in the semiconductor industry. One type of power MOSFET is a DMOS (double-diffused metal oxide semiconductor) transistor. A cross-sectional view of a portion of a cell array of one known variety of DMOS transistors is shown in
Upon applying a positive voltage to the gate and the drain, and grounding the source and the body regions, the channel region is inverted. A current thus starts to flow from the drain to the source through the drift region and the surface channel region.
A maximum forward blocking voltage, hereinafter referred to as “the breakdown voltage”, is determined by the avalanche breakdown voltage of a reverse-biased body-drain junction. The DMOS structure in
A drawback of the
The breakdown voltage of power MOSFETs is dependent not only upon the cell structure but also on the manner in which the device is terminated at its outer edges. To achieve a high breakdown voltage for the device as a whole, the breakdown voltage at the outer edges must be at least as high as that for the cells. Thus, for any cell structure, a corresponding terminating structure is needed which exhibits a high breakdown voltage.
In most amplifier circuits a significant amount of heat energy is produced in the transistor. Only 50% efficiency is typical of the best class AB RF power amplifiers available. An important factor in designing power devices for high frequency applications is thus the thermal performance of the device. Because of the different device performance requirements, the cells in power MOSFETs are densely packed resulting in concentration of heat in active regions and poor heat transfer rates. The increase in temperature resulting from the poor heat transfer rate adversely effects the device performance.
Thus, a power MOSFET device with such improved characteristics as low output capacitance, high breakdown voltage, and improved thermal performance is desired.
BRIEF SUMMARY OF THE INVENTIONIn accordance with the present invention, MOSFET cell structures and edge termination structures, and methods of manufacturing the same, are described which among other features and advantages exhibit a substantially reduced output capacitance, high breakdown voltage, and improved thermal performance.
In one embodiment, a MOSFET comprises at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.
In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, a first trench region extending from the first surface into the first semiconductor region, and at least one floating discontinuous region along a sidewall of the first trench region.
In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, a first trench region extending from the first surface into the first semiconductor region, and a first plurality of regions along a sidewall of the first trench region.
In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, and first and second insulation-filled trench regions each extending from the first surface into the first semiconductor region. Each of the first and second insulation-filled trench regions has an outer layer of silicon of a conductivity type opposite that of the first semiconductor region. The first and second insulation-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween such that the volume of each of the first and second trench regions is greater than one-quarter of the volume of the drift region.
In another embodiment, a MOSFET comprises a first semiconductor region over a substrate. The first semiconductor region has a first surface. The MOSFET further includes first and second insulation-filled trench regions each extending from the first surface to a predetermined depth within the first semiconductor region. Each of the first and second insulation-filled trench regions has an outer layer of doped silicon material which is discontinuous along a bottom surface of the insulation-filled trench region so that the insulation material along the bottom surface of the insulation-filled trench region is in direct contact with the first semiconductor region. The outer layer of silicon material is of a conductivity type opposite that of the first semiconductor region.
In another embodiment, a MOSFET comprises a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material are insulated from the first semiconductor region.
In accordance with an embodiment of the present invention, a MOSFET is formed as follows. A first epitaxial layer is formed over a substrate. A first doped region is formed in the first epitaxial layer. The first doped region has a conductivity type opposite that of the first epitaxial layer. A second epitaxial layer is formed over the first doped region and the first epitaxial region. A first trench region is formed which extends from a surface of the second epitaxial layer through the first and second epitaxial layers and the first doped region such that the first doped region is divided into two floating discontinuous regions along sidewalls of the first trench region.
In another embodiment, a MOSFET is formed as follows. A first epitaxial layer is formed over a substrate. First and second doped regions are formed in the first epitaxial layer. The first and second doped regions have a conductivity type opposite that of the first epitaxial layer. A second epitaxial layer is formed over the first and second doped regions and the first epitaxial region. First and second trench regions are formed wherein the first trench region extends through the first and second epitaxial layers and the first doped region such that the first doped region is divided into two floating discontinuous regions along sidewalls of the first trench region, and the second trench region extends through the first and second epitaxial layers and the second doped region such that the second doped region is divided into two floating discontinuous regions along sidewalls of the second trench region.
In another embodiment, a MOSFET is formed as follows. A first trench is formed in a first semiconductor region. A first doped region is formed along a bottom of the first trench. The first trench is extended deeper into the first semiconductor region such that of the first doped region two floating discontinuous regions remain along sidewalls of the first trench.
In another embodiment, a MOSFET is formed as follows. A first semiconductor region is formed over a substrate. The first semiconductor region has a first surface. A first trench is formed which extends from the first surface to a predetermined depth within the first semiconductor region. A layer of doped silicon material is formed along sidewalls of the trench. The layer of doped silicon material is of a conductivity type opposite that of the first semiconductor region.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.
MOSFET cell structures, edge termination structures, and methods of manufacturing the same are described in accordance with the present invention. Among other features and advantages, the cell and termination structures and methods of manufacturing the same exhibit a substantially reduced output capacitance, high breakdown voltage, and improved thermal performance.
Polysilicon gates 216 overlap source regions 212a,b, extend over the surface area of body regions 208a,b and over the surface area of epitaxial region 202 between body regions 208a and 208b. Gates 216 are insulated from the underlying regions by gate oxide 214. The surface area of body regions 208a,b directly under gates 216 form the channel regions. Metal layer 218 overlies the top-side of the structure and forms the common source-body contact.
The area of the epitaxial region between trenches 204a and 204b is hereinafter referred to as drift region 209. When proper biasing is applied to the gate, drain, and source terminals to turn on the device, current flows between drain terminal 203 and source terminal 207 through drain contact region 200, drift regions 209, the channel regions, source diffusion regions 212a,b, and finally metal layer 218.
Comparing
As described above, the polysilicon in the trenches of the prior art
Floating p regions 206a,b have the adverse effect of reducing the width of drift regions 209 through which current flows when the device is in the on-state, and thus result in increased on-resistance. However, the adverse impact of the floating p regions on the on-resistance can be reduced by obtaining an optimum balance between the charge concentration in the drift region and such features of the floating p regions as size, doping concentration, and the spacing Lp between them. For example, a higher charge concentration in the drift region would require a smaller spacing Lp and vice versa. Further, because the floating p regions reduce the electric field near the surface in the channel, the channel length can be reduced to improve the on-resistance and the general performance of the device as a high frequency amplifier.
In one embodiment wherein a breakdown voltage of 80-100V is desired, epitaxial region 202 has a doping concentration in the range of 5×1015 to 1×1016 cm−3 and the floating p regions 206a,b have a doping concentration of about 5-10 times that of the epitaxial region.
In
In
In
After preparation of the trench surface, a relatively thin insulator (e.g., about 300-500 Å of thermal oxide) is grown on the trench surface. Trenches 322a,b are then filled with a dielectric material such as silicon-dioxide using conventional conformal coating method and/or Spin-On Glass (SOG) method. Any low k dielectric to reduce the output capacitance may be used to fill trenches 322a,b. Conventional process steps used in forming self-aligned gate DMOS structures are then carried out to form the gate structure as shown in
An alternate method of manufacturing the structure in
Referring back to
To achieve effective vertical charge control, spacing Lp (
Two ways of achieving the increased Lc spacing while keeping Lp spacing the same are shown in
An advantage of the
Although
In
An exemplary set of process steps for forming the structure of
From the above, it can be seen that manufacturing of the
The doping concentration in the p liners/strips in
In
In
In
The semi-insulating strips in the structures of
An exemplary set of process steps for forming the structure in
The depth of the trenches in the different embodiments described above may vary depending on the desired device performance and the target application for the device. For example, for high breakdown voltage (e.g., greater than 70V), the trenches may be extended deeper into the epitaxial region (e.g., to a depth of about 5 μm). As another example, the trenches can be extended all the way through the epitaxial region to meet the substrate regions (as in
Although the trench structures in the different embodiments described above are shown in combination with the gate structure of conventional DMOS cells, the invention is not limited as such. Two examples of other gate structures with which these trench structures may be combined are shown in
The
Combining the gate structures in
In the above embodiments, the vertical charge control enabled by the resistive elements located along the insulation-filled trenches allows the cells to be laterally spaced apart without impacting the electrical characteristics of the device. With the cells spaced further apart, the heat generated by each cell is distributed over a larger area and less heat interaction occurs between adjacent cells. A lower device temperature is thus achieved.
Although the above embodiments show the drain to be located along the bottom-side of the die, the invention is not limited as such. Each of the above cell structures can be modified to become a quasi-vertically conducting structure by including a highly-doped n-type buried layer extending along the interface between the epitaxial region and the underlying highly-doped substrate region. At convenient locations, the buried layer is extended vertically to the top surface where it can be contacted to form the drain terminal of the device. In these embodiments, the substrate region may be n-type or p-type depending on the application of the MOSFET.
As mentioned earlier, edge termination structures with breakdown voltages equal to or greater than that of the individual cells are required to achieve a high device breakdown voltage. In the case of the
In
In another embodiment, the gate structure is included between trenches 1306b and 1306c, with spacing Lt equaling spacing Lc. In this embodiment, the p strip immediately to the right of the gate structure between trenches 1306b and 1306c (i.e., the p strip corresponding to the strip along the left side of trench 1306c) is not connected to the source and thus floats.
Other variations of the
Although the above-described termination structures are shown in combination with the cell structure in
While the above is a complete description of the embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, the different embodiments described above are n-channel power MOSFETs. Designing equivalent p-channel MOSFETs would be obvious to one skilled in the art in light of the above teachings. Further, p+ regions, similar to p+ regions 210a,b in the
Claims
1.-38. (canceled)
39. A MOSFET comprising:
- a first semiconductor region having a first surface;
- a first insulation-filled trench region extending from the first surface into the first semiconductor region, the first insulation-filled trench region having sidewalls and a bottom surface;
- strips of semi-insulating material extending along the sidewalls of the first insulation-filled trench region but not over at least a center portion of the bottom surface of the first insulation-filled trench region, the strips of semi-insulating material being insulated from the first semiconductor region; and
- an insulating material extending over at least the center portion of the bottom surface of the first insulation-filled trench region.
40. The MOSFET of claim 39 further comprising:
- a second insulation-filled trench region extending from the first surface into the first semiconductor region, the second insulation-filled trench region having sidewalls and a bottom surface, the second insulation-filled trench region having strips of semi-insulating material extending along its sidewalls but not over at least a center portion of the bottom surface of the second insulation-filled trench region, the strips of semi-insulating material being insulated from the first semiconductor region, the second insulation-filled trench region having an insulating material extending over at least the center portion of the bottom surface of the second-insulation-filled trench region,
- wherein the first and second insulation-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween, the volume of each of the first and second insulation-filled trench regions being greater than one-quarter of the volume of the drift region.
41. The MOSFET of claim 39 further comprising:
- a body region extending from the first surface into the first semiconductor region, the body region being of a conductivity type opposite that of the first semiconductor region;
- a source region in the body region, the source region being of the same conductivity type as the first semiconductor region;
- a second trench region extending from the first surface into the first semiconductor region; and
- a gate in the second trench region extending across a portion of the body region and overlapping the source and the first semiconductor regions such that a channel region extending perpendicularly to the first surface is formed in the body region between the source and first semiconductor regions.
42. The MOSFET of claim 39 further comprising:
- first and second body regions each extending from the first surface into the first semiconductor region, the first body region being laterally spaced from the second body region to form a JFET region therebetween, the first and second body regions being of a conductivity type opposite that of the first semiconductor region; and
- first and second source regions in the first and second body regions respectively, the first and second source regions being of the same conductivity type as the first semiconductor region.
43. The MOSFET of claim 42 further comprising a gate extending over but being insulated from the JFET region and a portion of the first and second body regions, and overlapping the first and second source regions such that a channel region is formed along a body surface of each of the first and second body regions between the corresponding source and JFET regions.
44. The MOSFET of claim 42 further comprising:
- a gate extending over but being insulated from each of the first and second body regions such that a channel region is formed along a surface of each of the first and second body regions between the corresponding source and JFET regions, the gate being discontinuous over a surface of the JFET region between the first and second body regions.
45. The MOSFET of claim 39 wherein the strips of semi-insulating material are from oxygen-doped polysilicon material.
46. The MOSFET of claim 39 further comprising a source region, wherein the strips of semi-insulating material are electrically connected to the source regions.
47. The MOSFET of claim 39 wherein each of the strips of semi-insulating material is insulated from its surrounding regions.
48. The MOSFET of claim 39 wherein each of the strips of semi-insulating material is floating.
49. The MOSFET of claim 39 further comprising a drain and a source, each of the strips of semi-insulating material being electrically coupled between the drain and the source.
50. The MOSFET of claim 39 further comprising a drain and a source, each of the strips of semi-insulating material being electrically coupled between the drain and the source so that during an operating mode of the MOSFET each of the strips of semi-insulating material acquires a linear voltage gradient from one end of the strip to an opposite end of the strip.
51. The MOSFET of claim 39 wherein:
- the first semiconductor region is over and in contact with a second semiconductor region of same conductivity type as the first semiconductor region, the second semiconductor region having a higher doping concentration than the first semiconductor region, and
- the strips of semi-insulating material extending through the first semiconductor region and terminating in the second semiconductor region.
52. The MOSFET of claim 39 wherein:
- the first semiconductor region is over and in contact with a second semiconductor region of same conductivity type as the first semiconductor region, the second semiconductor region having a higher doping concentration than the first semiconductor region, and
- the first insulation-filled trench extending through the first semiconductor region and terminating in the second semiconductor region.
53-71. (canceled)
72. The MOSFET of claim 39 wherein a resistivity of at least one of the strips of semi-insulating material varies from one end of the strip to an opposite end of the strip proximal the bottom surface of the first insulation-filled trench region.
Type: Application
Filed: May 24, 2011
Publication Date: Nov 24, 2011
Applicant: Fairchild Semiconductor Corporation (San Jose, CA)
Inventors: Steven Sapp (Felton, CA), Peter H. Wilson (Boulder Creek, CA)
Application Number: 13/114,253
International Classification: H01L 27/092 (20060101);