IGBT TRANSISTOR WITH PROTECTION AGAINST PARASITIC COMPONENT ACTIVATION AND MANUFACTURING PROCESS THEREOF
An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region.
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This application is a continuation of U.S. application Ser. No. 12/300,136 filed Nov. 10, 2008, which application is a national phase of International patent application number PCT/IT2006/000350 filed on 11 May 2006, which application is hereby incorporated by reference to the maximum extent allowable by law.
TECHNICAL FIELDThe present invention relates to an IGBT transistor with protection against activation of parasitic components and to a manufacturing process thereof.
BACKGROUND ARTAs is known, in IGBT transistors the maximum current in the conduction state is limited by the presence of an intrinsic parasitic thyristor. For greater clarity, reference may be made to
From an electrical standpoint, the body region 3, the drift region 2, and the collector region 13 define a PNP transistor 17, controlled by an NMOS transistor 18 formed by the source regions 5, the body region 3 (in particular, the channel regions 10) and the drift region 2. In addition, a further parasitic NPN transistor 19 is present, formed by the source regions 5, the body region 3 (outside the channel regions 10) and, once again, the drift region 2. In practice, the PNP transistor 17, the MOS transistor 18 and the NPN transistor 19 form a thyristor 20. In use, the current of the IGBT transistor 1 is substantially determined by a conduction current ID (of holes, in this case) of the PNP transistor 17 and by a control current IC (of electrons), which flows through the NMOS transistor 18. The NPN transistor 19 should be normally off. The body region 3, however, has a low doping level and hence a relatively high internal resistance RI. Consequently, the conduction current ID may cause a voltage drop between the source regions 5 and the body region 3 (which form the emitter and the base, respectively, of the NPN to transistor 19) such as to turn the NPN transistor 19 on. In this case, the thyristor 20 is activated, and the current flows directly towards the emitter line 7, independently of the MOS transistor 18, and hence can no longer be controlled by means of the gate terminal 11. In addition, activation of the transistor 20 limits the maximum current of the IGBT transistor 1, especially at high temperatures.
In order to overcome this problem, it has been proposed to reduce the resistance of the body region 3 by means of deep diffusion of a dopant species. In particular, the treatment concerns that portion of the body region 3 where mainly the conduction current ID is present. The dopant species is introduced through the openings between the gate regions 8 and diffuses towards the drift region 2. However, the diffusion is substantially isotropic and hence can easily alter doping of the channel region 10, in effect increasing the threshold voltage of the MOS transistor 18. The phenomenon hence limits the depth that the diffusion can reach and, consequently, also the benefit that can be achieved.
According to an alternative solution, a shallow implantation self-aligned to the gate regions 20 is performed and is followed by a diffusion for a short time. In this way, doping of the channel regions 10 and the value of the threshold voltage of the MOS transistor 18 are preserved, but it is possible to obtain only a modest reduction in the resistance of the body region 3.
SUMMARY OF THE INVENTIONAccording to one embodiment, the present invention provides an IGBT transistor and a manufacturing process thereof which will overcome at least some of the limitations described.
According to one embodiment, there is provided an IGBT transistor comprising a drift region, at least one body region housed in said drift region and having a first type of conductivity, and a conduction region crossing said body region in a direction perpendicular to a surface of said drift region and having said first type of conductivity and a lower resistance than said body region, characterized in that said conduction region comprises a plurality of implant regions arranged at respective depths from said surface of said drift region and a process for manufacturing an IGBT transistor comprising the steps of providing, in a semiconductor wafer, a drift region forming, in said drift region, at least one body region having a first type of conductivity, and forming a conduction region crossing said body region in a direction perpendicular to a surface of said drift region and having said first type of conductivity and a resistance lower than that of said body region, characterized in that said step of forming said conduction region comprises carrying out a plurality of implantations of dopant species in said body region at respective depths from said surface of said drift region.
For a better understanding of the invention, an embodiment thereof will now be described, purely by way of non-limiting example, with reference to the attached drawings, wherein:
With reference to
As is shown in
Next (
The first mask 108 is removed, and in its place a second mask 114 is provided, as shown in
Then, an N+-type implantation is carried out using the second mask 114. In this step, through the second windows 115 of the second mask 115, source regions 117 of an N+-type are formed, having, for example, a level of doping of 1020 atoms/cm3. In each body region 112 two source regions 117 are made, aligned to respective gate regions 110. The channel regions 113 are defined between the source regions 117 and the drift region 103, immediately underneath the gate-oxide regions 105a.
With reference to
Using the third mask 118, a surface implantation of a P+-type is first carried out so as to create a surface implant region 121 of a P+-type, having approximately the same doping level as the source regions 117 (approximately 1020 atoms/cm3), but opposite conductivity. Furthermore, the energy of the implantation is such that the peak of the doping density of the surface implant region 121 is found slightly underneath the source regions 117.
As shown in
In detail (
The buried implant regions 123a-123d are arranged at increasing depths, are contiguous to one another and moreover have an intermediate doping level between the body region 112 and the surface implant region 121 (for example, approximately 1019 atoms/cm3). Consequently, the conduction region 124, comprising the buried implant regions 123a-123d and the surface implant region 121, defines a continuous conductive path through the body region 112 in a direction perpendicular to the surface 103a of the drift region 103. The conduction region 124 has a resistance smaller than the body region 112.
At the end of the sequence of implantations, the third mask 118 is removed, and an ultra-rapid thermal process is carried out, for example bringing the wafer 100 to a temperature of between 1000° C. and 1150° C. for 10-30 s. During the ultra-rapid thermal process, the dopant species introduced into the wafer 100 are electrically activated, but do not have enough time to diffuse and consequently remain where they are.
With reference to
Then, a metal layer is deposited and delineated by a photolithographic process in order to provide an emitter line 126, which extends within the openings 110 and electrically connects to the body regions 112 and the source regions 117 to one another. In addition, also a gate line 127 is defined, connected to the gate regions 107a (
Finally (
The process described advantageously enables provision of an IGBT transistor in which latch-up of the intrinsic parasitic thyristor requires a particularly high current density. In fact, the highly conductive paths traversing entirely the body regions 112 enable drawing high currents without causing any significant voltage drops between the body regions 112 themselves and the source regions 117 housed therein.
In addition, doping of the channel regions 113 is preserved. The deep implantations are, in fact, carried out maintaining a margin of distance from the respective gate regions 107, which delimit the channel regions 113. The dopant species introduced into the body regions are subjected to inevitable phenomena of scattering associated to the implantation, and hence the surface implant region 121 and deep implant regions 123a-123b can be slightly misaligned with respect to the third mask 118. However, the margin of distance is sufficient to prevent the dopant species from reaching the channel regions 113, thus maintaining the doping substantially unaltered. Consequently, also the threshold voltage can be controlled easily.
Finally, it is evident that modifications and variations can be made to the IGBT transistor and to the manufacturing process described herein, without departing from the scope of the present invention, as defined in the annexed claims.
In particular, the conductive path through the body regions 112 can be obtained by an arbitrary number of implantations. In addition, the deep implants could be obtained starting from the deepest, then decreasing the implantation energy, or even in any other arbitrary order.
Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.
Claims
1. An IGBT transistor comprising:
- a drift region;
- at least one body region housed in said drift region and having a first type of conductivity; and
- a conduction region, crossing said body region in a direction perpendicular to a surface of said drift region and having said first type of conductivity and a lower resistance than said body region;
- characterized in that wherein said conduction region comprises a plurality of implant regions, arranged at respective depths from said surface of said drift region.
2. The transistor according to claim 1, wherein said implant regions comprise a surface implant region and a plurality of buried implant regions contiguous to one another.
3. The transistor according to claim 2, wherein one of said deep implant regions is contiguous to said drift region.
4. The transistor according to claim 2, wherein said conduction region has a higher doping level than said body region.
5. The transistor according to claim 4, wherein said deep implant regions have an intermediate doping level between said body region and said surface implant region.
6. The transistor according to claim 1, wherein said drift region has a second type of conductivity, opposite to said first type of conductivity.
7. The transistor according to claim 6, comprising at least one source region housed in said body region and having said second type of conductivity.
8. The transistor according to claim 7, comprising gate regions arranged on said drift region and defining an opening above said conduction region.
9. The transistor according to claim 8, wherein said conduction region is arranged centrally with respect to said opening.
10. The transistor according to claim 8 or claim 9, wherein said body region extends around said opening and is separated from said gate regions by gate-oxide regions and wherein portions of said body region immediately underlying said gate-oxide regions define channel regions.
11. A process for manufacturing an IGBT transistor, comprising the steps of:
- providing, in a semiconductor wafer, a drift region;
- forming, in said drift region, at least one body region having a first type of conductivity; and
- forming a conduction region, crossing said body region in a direction perpendicular to a surface of said drift region and having said first type of conductivity and a resistance lower than that of said body region;
- characterized in that wherein said step of forming said conduction region comprises:
- carrying out a plurality of implantations of dopant species in said body region at respective depths from said surface of said drift region.
12. The process according to claim 11, wherein said step of carrying out a plurality of implantations comprises carrying out a surface implantation for forming a surface implant region and a plurality of deep implantations for providing respective deep implant regions.
13. The process according to claim 12, wherein said conduction region has a higher doping level than said body region.
14. The process according to claim 13, wherein said deep implant regions have an intermediate doping level between said body region and that of said surface implant region.
15. The process according to claim 11, wherein said drift region has a second type of conductivity, opposite to said first type of conductivity.
16. The process according to claim 11, comprising the step of subjecting said semiconductor wafer to a thermal process for electrically activating the implanted dopant species, wherein said thermal process has a duration such as to prevent diffusion of the implanted dopant species.
17. The process according to claim 16, wherein a duration of said thermal process is between 10 s and 30 s.
18. The process according to claim 16, wherein said thermal process comprises to heating said wafer up to a temperature of between 1000° C. and 1150° C.
19. The process according to claim 16, comprising the steps of:
- forming a gate-oxide layer on said drift region;
- depositing a conductive polysilicon layer on said gate-oxide layer; and
- shaping said conductive layer and said gate-oxide layer for forming gate regions, separated from said drift region by respective gate-oxide regions and defining openings above said drift region.
20. The process according to claim 19, wherein said step of forming said body region comprises:
- introducing dopant species into said drift region through said openings; and
- diffusing the dopant species introduced.
Type: Application
Filed: Aug 17, 2011
Publication Date: Jan 5, 2012
Applicant: STMicroelectronics S.r.l. (Agrate Brianza (MI))
Inventors: Davide Giuseppe Patti (Mascalucia), Giuditta Settanni (Catania)
Application Number: 13/211,650
International Classification: H01L 29/739 (20060101); H01L 21/331 (20060101);