METHOD OF OPERATING A PHASE-CHANGE MEMORY DEVICE
A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.
This U.S. nonprovisional application is a continuation under 35 U.S.C. §120 of U.S. application Ser. No. 12/081,451, filed on Apr. 16, 2008, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0122737, filed on Nov. 29, 2007 in the Korean Intellectual Property Office, the disclosure of each of which is hereby incorporated herein in their entirety by reference.
BACKGROUND1. Field
Example embodiments relate to a method of operating a memory device. Other example embodiments relate to a method of operating a phase-change memory device.
2. Description of the Related Art
There are several types of non-volatile memory devices including a flash memory, a ferroelectric RAM (FeRAM), a magnetic RAM (MRAM) and phase-change random access memories (PRAMs). A storage node of a PRAM is structurally different than other non-volatile memory devices.
A storage node of a PRAM includes a phase-change layer as a data storage layer. If a predetermined reset voltage is applied to the phase-change layer for a substantially short amount of time, a region of the phase-change layer changes to an amorphous region. If a predetermined set voltage is applied to the storage node for a substantially long amount of time, the amorphous region returns to a crystalline state.
Assuming that a first resistance pertains to the phase-change layer having an amorphous region and a second resistance pertains to the phase-change layer having no amorphous region, the first resistance is higher than the second resistance.
The PRAM is a memory device that writes and reads bit data using a phase-change layer having resistance characteristics that vary depending on the phase of the phase-change layer.
A conventional method of operating the PRAM may have a substantially slow operation speed because a set amount of time for the amorphous region to return to the crystalline state is relatively long.
In the conventional method of operating the PRAM, the characteristics of the phase-change layer may easily deteriorate by repeating the reset and set operations, shortening the durability (or endurance) of the PRAM.
SUMMARYExample embodiments relate to a method of operating a memory device. Other example embodiments relate to a method of operating a phase-change memory device.
Example embodiments provide a method of operating a phase-change memory device using a phase change layer having resistance characteristics that vary depending on a phase of the phase-change layer.
According to example embodiments, there is provided a method of operating a phase-change memory device having a phase-change layer and a unit applying a voltage to the phase-change layer, the method including applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied. The pulse voltages may be substantially the same.
A pulse width of each of the pulse voltages may be less than 20 ns. A pulse width of each of the pulse voltages may range from 5 ns to 20 ns. An interval between the pulse voltages may be less than 100 ns. The interval between the pulse voltages may be greater than 5 ns. The interval between the pulse voltages may range from 5 ns to 100 ns. The number of the pulse voltages may range 2 to 10.
The method may include applying a set voltage to the phase-change layer, after the applying of the reset voltage to the phase-change layer.
The reset voltage may be applied for an equal or less amount of time than the set voltage.
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
Detailed illustrative embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.
Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of example embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient (e.g., of implant concentration) at its edges rather than an abrupt change from an implanted region to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation may take place. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
In order to more specifically describe example embodiments, various aspects will be described in detail with reference to the attached drawings. However, the present invention is not limited to example embodiments described.
Example embodiments relate to a method of operating a memory device. Other example embodiments relate to a method of operating a phase-change memory device.
Referring to
The phase of a region of the phase-change layer 30 contacting the lower electrode contact layer 20 may be changed according to a voltage V applied between the lower electrode 10 and the upper electrode 40. The overall phase-change layer 30 shown in
Referring to
Magnitudes of the first, second and third pulse voltages V1, V2, V3 may be the same. First, second and third pulse widths T1, T2, T3, for which the first, second and third pulse voltages V1, V2, V3, respectively, are applied may be the same. As such, the first, second and third pulse voltages V1, V2, V3 may be substantially the same. Each of the first, second and third pulse widths T1, T2, T3 may be less than 20 nanoseconds (ns). Each of the first, second and third pulse widths T1, T2, T3 may range from 5 ns to 20 ns. A first interval I1 between the first pulse voltage V1 and second pulse voltage V2 and a second interval I2 between the second pulse voltage V2 and third pulse voltage V3 may, or may not, be equal to each other. Each of the first interval I1 and second interval I2 may be less than 100 ns. Each of the first interval I1 and second interval I2 may range from 5 ns to 100 ns.
If such short pulse voltages are continuously applied at predetermined intervals, the region of the phase-change layer 30 contacting the lower electrode contact layer 20 may change to an amorphous region. For example, if the reset voltage Vreset of
Referring to
A local region of the phase-change layer 30 may melt due to the first pulse voltage V1 and cool for a time corresponding to the first interval I1 to become an amorphous region. The amorphous local region may be one of the first, second or third regions a1, a2, a3. For example, the amorphous local region may be the second region a2. If the second region a2 is an amorphous region, the second region a2 has a resistivity higher than crystalline regions around the amorphous region a2. If the second pulse voltage V2 is applied between the lower electrode 10 and the upper electrode 40, current flows through the crystalline regions around the amorphous local region (e.g., second region a2), heating a portion of the crystalline regions. One (e.g., the first region a1) of the other two regions (e.g., the first region a1 and the third region a3) may be formed from the heated regions. The remaining region (e.g., third region a3) may be formed by the third pulse voltage V3.
Although the reset voltage Vreset includes the first, second and third pulse voltages V1, V2, V3 in
Referring to
If the reset voltage V′reset of
Referring to
A region of the phase-change layer 30 is heated by the reset voltage V′reset of
Because the first, second and third regions a1, a2, a3 of
Because a method of operating a PRAM according to example embodiments may prevent (or reduce) the phase-change layer from being excessively heated during a reset operation, the durability of the PRAM may increase. If a region of a phase-change layer becomes an amorphous region by excessively heating and cooling, it may be difficult to return the amorphous region to a crystalline region, increasing the set time. In a method of operating a PRAM according to example embodiments, the PRAM has a shorter set time because the phase-change layer is not excessively heated during a reset operation.
In a method of operating a PRAM according to example embodiments, because a resistance of the phase-change layer is not measured between the pulse voltages applied during the reset operation, time necessary for measuring the resistance decreases.
Referring to
Referring to
A set time of a PRAM according to example embodiments is more than 100 ns, which is longer than a reset time. A programming time is determined by the set time that is longer than the reset time. Even though a reset time T1+I1+T2+I2+T3 of
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
Claims
1. A method of programming a memory device having a resistance-change layer, a first electrode contact layer, and a unit applying a voltage to the resistance-change layer, the programming method comprising:
- applying a reset voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a resistance-change is initiated at a surface of the resistance-change layer contacting the first electrode contact layer,
- wherein the reset voltage includes at least two pulse voltages.
2. The method of claim 1, wherein the at least two pulse voltages are sequentially applied.
3. The method of claim 1, wherein the at least two pulse voltages are continuously applied.
4. The method of claim 1, wherein the at least two pulse voltages are applied with a time interval therebetween.
5. The method of claim 1, wherein the at least two pulse voltages are applied with identical magnitude.
6. The method of claim 1, wherein a pulse width of the at least two pulse voltages are equal.
7. The method of claim 1, further comprising:
- applying a set voltage to the resistance-change layer,
- wherein the set voltage includes one pulse voltage.
8. A method of programming a memory device having a resistance-change layer, a first electrode contact layer, and a unit applying a voltage to the resistance-change layer, the programming method comprising:
- applying a reset voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a resistance-change is initiated at a surface of the resistance-change layer contacting the first electrode contact layer, wherein the reset voltage includes at least two pulse voltages; and
- applying a set voltage to the resistance-change layer.
9. The method of claim 8, wherein the reset voltage is applied for an equal or shorter amount of time than the set voltage.
10. The method of claim 8, wherein the set voltage includes one pulse voltage.
11. The method of claim 8, wherein the applying a reset voltage to the resistance-change layer includes,
- applying a first pulse voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a first resistance-change is initiated at a first surface of the resistance-change layer contacting the first electrode contact layer; and
- applying a second pulse voltage to the resistance-change layer via the first electrode contact layer in the programming step for data writing such that a second resistance-change is initiated at a second surface of the resistance-change layer contacting the first electrode contact layer, wherein the second surface is disposed adjacent to the first surface.
12. The method of claim 8, wherein the at least two pulse voltages are sequentially applied in a same programming step.
13. The method of claim 8, wherein the at least two pulse voltages are continuously applied in a same programming step.
14. The method of claim 8, wherein the at least two pulse voltages are applied with a time interval therebetween in a same programming step.
15. The method of claim 8, wherein the at least two pulse voltages are applied with identical magnitude.
16. The method of claim 8, wherein a pulse width of the at least two pulse voltages are equal.
Type: Application
Filed: Jan 4, 2012
Publication Date: Apr 26, 2012
Inventors: Cheol-kyu KIM (Seoul), Yoon-ho Khang (Yongin-si), Ki-joon Kim (Hwaseong-si)
Application Number: 13/343,383
International Classification: G11C 11/21 (20060101);