ON-DEMAND TABLE MODEL FOR SEMICONDUCTOR DEVICE EVALUATION

Abstract

An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

Description

FIELD OF THE INVENTION

The invention relates to semiconductor devices and methods of evaluation and, more particularly, to an on-demand table model for semiconductor device evaluation.

BACKGROUND

To evaluate semiconductor device models, there are several known processes. For example, in a process using linear table models, multi-dimensional grids can be populated with measurement (e.g., currents and/or charges as functions of terminal voltages) values of semiconductor device models. Linear interpolation may then be utilized to generate, e.g., current and/or charge values for a circuit simulator which needs device evaluations during its operation. In another example, higher order polynomial function table models may be used that rely on multiple grid points from neighboring regions to build and solve polynomial equations representing, e.g., the current and/or charge values.

However, the known processes for semiconductor device evaluation include several issues. For example, in the linear table model process, when the linear interpolation generates a first order derivative, the resulting current and/or charge values may not be continuous across boundaries of the multi-dimensional grids. This lack of continuity across the boundaries causes simulation difficulties for the circuit simulator. In the higher order polynomial function table model process, a non-uniform grid including a high amount of sample points may be required that is costly to generate and manage to ensure that the polynomial equations and their derivatives follow the measurement data closely. For all known processes, a circuit simulator's knowledge of evaluation equations may also be required, and may have to be set and inflexible for evaluation. In addition, the known processes may consume an exorbitant amount of memory and/or processing capabilities during evaluation due to the complexity of the higher order polynomial function table models.

Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

SUMMARY

In a first aspect of the invention, a method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon measurement of the one or more measurement values. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

In another aspect of the invention, a computer program product includes a tangible computer usable storage medium having readable program code embodied in the tangible computer usable storage medium. The computer program product further includes at least one component operable to measure one or more measurement values of an instance of a semiconductor device. The at least one component is further operable to provide a table model of the instance for semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The at least one component is further operable to generate a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

In yet another aspect of the invention, a method for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes at least one of retrieving and generating, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation based on whether the table model is assigned to the instance. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including a plurality of coefficients of a Hermite spline function for the instance.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

FIG. 1 is an exemplary environment for implementing the steps in accordance with aspects of the invention;

FIGS. 2-3 are exemplary flow diagrams of processes of providing on-demand table models for semiconductor device evaluation in accordance with aspects of the invention;

FIG. 4 is an exemplary grid of semiconductor voltages for which a table model for semiconductor device evaluation is provided in accordance with aspects of the invention;

FIG. 5 are exemplary grids of voltages for which a table model of a n-type field effect transistor (nFET) in an inverter is provided and evaluated in accordance with aspects of the invention;

FIG. 6 are exemplary grids of voltages for which a table model of the nFET in a plurality of inverters is provided and evaluated in accordance with aspects of the invention; and

FIG. 7 are exemplary grids of voltages for which a table model of the nFET in a plurality of logic gates is provided and evaluated in accordance with aspects of the invention.

DETAILED DESCRIPTION

The invention relates to semiconductor structures and methods of evaluation and, more particularly, to an on-demand table model for semiconductor device evaluation. More specifically, the present invention includes a table model tool for providing on-demand table models for semiconductor device evaluation or simulation when they are needed during the semiconductor device evaluation or simulation. The table model tool further provides continuous evaluation function values for the table models using a Hermite spline function which requires only information local to a certain measurement point in the table models.

In embodiments, the table model tool can measure or receive a plurality of measurement values (e.g., voltages) of a known particular instance (e.g., type) of a semiconductor device. For example, the semiconductor device may include a metal-oxide-semiconductor field-effect transistor (MOSFET) of n- or p-type, a n-type field effect transistor (nFET), a p-type field effect transistor (pFET), and/or other types of semiconductor devices. The measurement values of the instance of the semiconductor device may include, for example, a source-to-bulk voltage v_sb, a gate-to-bulk voltage v_gb, and drain-to-bulk voltage v_db, of a specific type of a MOSFET. Upon request for an evaluation of a table model of an instance of the semiconductor device, the table model tool may provide (e.g., retrieve or generate) the on-demand table model of the instance of the semiconductor device. The table model may include a multi-dimensional (e.g., three-dimensional) grid of previously-measured measurement points of the instance of the semiconductor device. For example, each of the measurement points may include a plurality of measurement values of the instance of the semiconductor device, such as voltages v_sb, v_gb, v_db of a specific type of a MOSFET. For each of the measurement points (e.g., (v_sb, v_gb, v_db)), the table model may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents, and/or charges) of an evaluation function (e.g., the Hermite spline function) for the instance of the semiconductor device.

In accordance with further aspects of the invention, when, in the table model, a corresponding table entry does not exist for the currently-measured measurement values of the instance of the semiconductor device, the table model tool can generate a table entry for the currently-measured measurement values. For example, the table model tool may generate a plurality of evaluation values (e.g., coefficients, currents, and/or charges) of an evaluation function (e.g., the Hermite spline function) based on the currently-measured measurement values, values local to the measurement values, and nonlinear equations related to the evaluation function. Based on the table model, the table model tool may evaluate the instance of the semiconductor device, e.g., determine and evaluate resulting values of the evaluation function for one or more of the measurement points to determine a quality of and/or simulate the instance of the semiconductor device.

Advantageously, the use of on-demand table models of the present invention reduces memory consumption by generating and saving table models only when they are needed for semiconductor device evaluation, instead of requiring predetermined models for all potential measurement values. Since the table models may have less measurement and evaluation values than traditional models, the table models may be easier to manage and manipulate, and may thus, result in optimal processing efficiency. The table models are further saved for later use, which allows the table model tool to bypass some of the difficult computations of the table models and thereby further increase processing efficiency.

In addition, the use of the Hermite spline function of the present invention provides fast evaluation of semiconductor devices with only a set of local measurement values while maintaining accuracy equivalent to traditional evaluation models, such as the Berkley Short-channel IGFET Model (BSIM). The Hermite spline function also allows for continuity of evaluation functions at cross-grid boundaries of the multi-dimensional measurement values, and for monotonicity (e.g., no artifacts) through the boundaries. Even further, the Hermite spline function and its resulting values may be determined independent of any predetermined evaluation function, making it flexible for storing and adapting to any various evaluation functions.

System Environment

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

FIG. 1 shows an illustrative environment 10 for managing the processes in accordance with the invention. To this extent, the environment 10 includes a server or other computing system 12 that can perform the processes described herein. In embodiments, the server 12 may include any mobile computing device, such as a mobile phone, a laptop, a video camera, etc. In particular, the server 12 includes a computing device 14. The computing device 14 can be resident on a network infrastructure or computing device of a third party service provider (any of which is generally represented in FIG. 1).

The computing device 14 also includes a processor 20, memory 22A, an I/O interface 24, and a bus 26. The memory 22A can include local memory employed during actual execution of program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. In addition, the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S).

The computing device 14 is in communication with an external I/O device/resource 28 and the storage system 22B. For example, the I/O device 28 can comprise any device that enables an individual to interact with the computing device 14 (e.g., user interface) or any device that enables the computing device 14 to communicate with one or more other computing devices using any type of communications link. The external I/O device/resource 28 may be for example, a handset, keyboard, etc.

In general, the processor 20 executes computer program code (e.g., program control 44), which can be stored in the memory 22A and/or storage system 22B. Moreover, in accordance with aspects of the invention, the program control 44 controls a table model tool 105, e.g., the processes described herein. The table model tool 105 can be implemented as one or more program code in the program control 44 stored in memory 22A as separate or combined modules. Additionally, the table model tool 105 may be implemented as separate dedicated processors or a single or several processors to provide the function of this tool. Moreover, it should be understood by those of ordinary skill in the art that the table model tool 105 is used as a general descriptive term for providing the features and/or functions of the present invention.

While executing the computer program code, the processor 20 can read and/or write data to/from memory 22A, storage system 22B, and/or I/O interface 24. The program code executes the processes of the invention, for example, functions of the table model tool 105, e.g., provide an on-demand table model for semiconductor device evaluation, using a Hermite spline function. The bus 26 provides a communications link between each of the components in the computing device 14.

In embodiments, the table model tool 105 can measure or receive a plurality of measurement values (e.g., voltages) of a known particular instance of a semiconductor device 110. For example, the semiconductor device 110 may include a metal-oxide-semiconductor field-effect transistor (MOSFET) of n- or p-type, a n-type field effect transistor (nFET), a p-type field effect transistor (pFET), and/or other types of semiconductor devices. The instance of the semiconductor device 110 may include a specific type of the semiconductor device 110 that can be represented by, e.g., a model name, a temperature, a corner or family name (e.g., MOSFET), and/or other instance parameters (e.g., a length, a width, etc.), of the semiconductor device 110. The measurement values of the instance of the semiconductor device 110 may include, for example, a source-to-bulk voltage v_sb, a gate-to-bulk voltage v_gb, and drain-to-bulk voltage v_db, of a specific type of a MOSFET.

In accordance with further aspects of the invention, upon receiving a request from a user for semiconductor device evaluation, the table model tool 105 can provide (e.g., retrieve or generate) an on-demand table model of the instance of the semiconductor device 110. In embodiments, the table model may include a multi-dimensional (e.g., three-dimensional) grid of previously-measured measurement points of the instance of the semiconductor device 110. For example, each of the measurement points may include a plurality of measurement values of the instance of the semiconductor device 110, such as voltages v_sb, v_gb, v_db of a specific type of a MOSFET. For each of the measurement points (e.g., (v_sb,v_gb,v_db)), the table model may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, a drain-to-source current I_ds, a drain-to-bulk current I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the instance of the semiconductor device 110. The table model tool 105 may either retrieve or generate the table model for the instance of the semiconductor device 110 based on whether a table model is assigned to (e.g., was previously-generated and stored for) the instance.

In embodiments, when, in the table model, a corresponding table entry does not exist for the currently-measured measurement values of the instance of the semiconductor device 110, the table model tool 105 can generate a table entry for the currently-measured measurement values. For example, the table model tool 105 can generate a plurality of evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) based on the currently-measured measurement values, local cubic values, and nonlinear equations, as described below. The table model tool 105 may store and/or update the generated evaluation values for later use in the table model which may be stored in, for example, the memory 22A and/or the storage system 22B. Based on the table model, the table model tool 105 can evaluate the instance of the semiconductor device 110, e.g., determine and evaluate resulting values of the evaluation function for one or more of the measurement points to determine a quality of and/or simulate the instance of the semiconductor device 110. If a generated table model causes a problem (e.g., an error, erroneous values, etc.) during semiconductor device evaluation and/or circuit simulation, the table model tool 105 may be instructed by a user to switch to a different type of analytical model (e.g., the original semiconductor model).

Advantageously, the table model tool 105 generates and stores table models, table entries, and/or evaluation values for values measured and to be evaluated in a semiconductor device, does not generate and store redundant table models, table entries, and/or evaluation values which are not used. Accordingly, use of the table model tool 105 decreases memory usage and increases processing performance in comparison to the known art. Further, by using cubic values local to measurement values of a semiconductor device to determine evaluation values of an evaluation function (e.g., a Hermite spline function), the table model tool 105 provides continuity of the evaluation values and function in a manageable table model. In addition, the table model tool 105 may be adapted for various instances or types of semiconductor devices.

The computing device 14 can comprise any general purpose computing article of manufacture capable of executing computer program code installed thereon (e.g., a personal computer, server, etc.). However, it is understood that the computing device 14 is only representative of various possible equivalent-computing devices that may perform the processes described herein. To this extent, in embodiments, the functionality provided by the computing device 14 can be implemented by a computing article of manufacture that includes any combination of general and/or specific purpose hardware and/or computer program code. In each embodiment, the program code and hardware can be created using standard programming and engineering techniques, respectively.

Similarly, the computing infrastructure 12 is only illustrative of various types of computer infrastructures for implementing the invention. For example, in embodiments, the server 12 comprises two or more computing devices (e.g., a server cluster) that communicate over any type of communications link, such as a network, a shared memory, or the like, to perform the process described herein. Further, while performing the processes described herein, one or more computing devices on the server 12 can communicate with one or more other computing devices external to the server 12 using any type of communications link. The communications link can comprise any combination of wired and/or wireless links; any combination of one or more types of networks (e.g., the Internet, a wide area network, a local area network, a virtual private network, etc.); and/or utilize any combination of transmission techniques and protocols.

FIGS. 2-3 show an exemplary flow for performing aspects of the present invention. The steps of FIGS. 2-3 may be implemented in the environment of FIG. 1, for example. The flowcharts and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. The software and/or computer program product can be implemented in the environment of FIG. 1. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable storage medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disc-read/write (CD-R/W) and DVD.

FIG. 2 depicts an exemplary flow for a process 200 of providing on-demand table models for semiconductor device evaluation in accordance with aspects of the invention. In embodiments, the process 200 can be performed by the table model tool 105 in FIG. 1. At step 205, the process starts. At step 210, the table model tool measures or receives a plurality of measurement values (e.g., voltages) of a known particular instance of a semiconductor device (e.g., the semiconductor device 110 in FIG. 1). For example, the semiconductor device 110 can include a metal-oxide-semiconductor field-effect transistor (MOSFET) of either type, a n-type field effect transistor (nFET), a p-type field effect transistor (pFET), and/or other types of semiconductor devices. The measurement values of the instance of the semiconductor device may include, for example, a source-to-bulk voltage v_sb, a gate-to-bulk voltage v_gb, and drain-to-bulk voltage v_db, of a specific type of a MOSFET.

At step 215, upon receiving a request for semiconductor device evaluation from a user, the table model tool provides (e.g., retrieve or generate) an on-demand table model of the instance of the semiconductor device. In embodiments, the table model can include a multi-dimensional (e.g., three-dimensional) grid of previously-measured measurement points of the instance of the semiconductor device. For example, each of the measurement points may include a plurality of measurement values of the instance of the semiconductor device, such as voltages v_sb, v_gb, v_db of a specific type of a MOSFET. For each of the measurement points (e.g., (v_sb,v_gb,v_db)), the table model may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the instance of the semiconductor device. The table model tool may either retrieve or generate the table model for the instance of the semiconductor device based on whether a table model is assigned to (e.g., was previously-generated and stored for) the instance.

At step 220, when, in the table model, a corresponding table entry does not exist for the currently-measured measurement values of the instance of the semiconductor device, the table model tool generates a table entry for the currently-measured measurement values. In embodiments, the table model tool can generate a plurality of evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) based on the currently-measured measurement values, local cubic values, and nonlinear equations, as described below. At step 225, based on the table model, the table model tool evaluates the instance of the semiconductor device, e.g., determine and evaluate resulting values of the evaluation function for one or more of the measurement points to determine a quality of and/or simulate the instance of the semiconductor device. At step 230, the process ends.

FIG. 3 depicts an exemplary flow for a process 300 of providing on-demand table models for semiconductor device evaluation in accordance with aspects of the invention. In embodiments, the process 300 can be performed by the table model tool 105 in FIG. 1. At step 305, the process starts. At step 310, the table model tool measures a plurality of measurement values (e.g., voltages) of a known particular instance of a semiconductor device (e.g., the semiconductor device 110 in FIG. 1). For example, the semiconductor device 110 can include a metal-oxide-semiconductor field-effect transistor (MOSFET) of either type, a n-type field effect transistor (nFET), a p-type field effect transistor (pFET), and/or other types of semiconductor devices. The measurement values of the instance of the semiconductor device may include, for example, a source-to-bulk voltage v_sb, a gate-to-bulk voltage v_gb, and drain-to-bulk voltage v_db, of a specific type of a MOSFET.

At step 315, upon receiving a request for semiconductor device evaluation from a user, the table model tool determines whether an on-demand table model is assigned to the particular instance of the semiconductor device. In embodiments, the table model can include a multi-dimensional (e.g., three-dimensional) grid of previously-measured measurement points of the instance of the semiconductor device. For example, each of the measurement points may include a plurality of measurement values of the instance of the semiconductor device, such as voltages v_sb, v_gb, v_db of a specific type of a MOSFET. For each of the measurement points (e.g., (v_sb,v_gb,v_db)), the table model may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the instance of the semiconductor device. If a table model is assigned to the instance of the semiconductor device, then the process continues at step 320. Otherwise, the process continues at step 325.

At step 320, the table model tool determines whether, in the table model assigned to the instance of the semiconductor device, a corresponding table entry exists for the currently-measured measurement values of the instance of the semiconductor device. If the table entry exists for the currently-measured measurement values, then the process continues at step 335. Otherwise, the process continues at step 330.

At step 330, the table model tool generates a table entry for the currently-measured measurement values. In embodiments, the table model tool can generate a plurality of evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) based on the currently-measured measurement values, local cubic values, and nonlinear equations, as described below. At step 335, based on the table model, the table model tool evaluates the instance of the semiconductor device, e.g., determine and evaluate resulting values of the evaluation function for one or more of the measurement points to determine a quality of and/or simulate the instance of the semiconductor device.

At step 325, the table model tool generates a key based on the instance of the semiconductor device. In embodiments, the instance of the semiconductor device may include a specific type of the semiconductor device that can be represented by, e.g., a model name, a temperature, a corner or family name (e.g., MOSFET), and/or other instance parameters (e.g., a length, a width, etc.), of the semiconductor device. The key may be generated based on the type of the semiconductor device, to find a stored table model assigned to another instance of a semiconductor device that includes the same type of semiconductor device. Such a table model may be subsequently assigned to the instance of the semiconductor device. That is, a table model may be assigned to a plurality of instances of semiconductor devices which are similar in type, e.g., MOSFETs.

At step 340, the table model tool determines whether the stored table model assigned to another instance of a semiconductor device is found based on the generated key. If such a table model is found, the process continues at step 360. Otherwise, the process continues at step 345.

At step 345, the table model tool determines whether a table model file exists in memory and/or a storage system, e.g., the memory 22A and/or the storage system 22B in FIG. 1. In embodiments, the table model file can include a predetermined table model which may be initially assigned to an instance of a semiconductor device without a table model already assigned. The predetermined table model may include predetermined measurement (e.g., voltage) values and evaluation (e.g., Hermite spline coefficient, current I_ds and I_db, and/or a charge Q_db) values, or may be unpopulated with values. If the table model file exists, the process continues at step 350. Otherwise, the process continues at step 355.

At step 350, the table model tool loads or retrieves a table model from the table model file in the memory and/or the storage system. At step 355, the table model generates or creates a table model. In embodiments, the generated table model may include predetermined measurement (e.g., voltage) values and evaluation (e.g., Hermit spline coefficient, current I_ds and I_db, and/or a charge Q_db) values, or may be unpopulated with values. At step 360, the table model tool assigns the found table model based on the generated key, the loaded table model from the table model file, and/or the generated table model to the instance of the semiconductor device. The process continues at step 320. At step 365, the process ends.

FIG. 4 is an exemplary grid 400 of semiconductor voltages for which a table model for semiconductor device evaluation is provided in accordance with aspects of the invention. In embodiments, the grid 400 can be for (e.g., assigned to) one or more instances of semiconductor devices of similar type (e.g., MOSFETs). The grid 400 may include a multi-dimensional (e.g., three-dimensional) grid with, for example, a first axis 405 of source-to-bulk voltages v_sb, a second axis 410 of gate-to-bulk voltages v_gb, and a third axis 415 of drain-to-bulk voltages v_db, of MOSFETs. The grid 400 may further include previously-measured measurement points (e.g., (x,y,z)) of the instances of the semiconductor devices. For example, each of the measurement points may include a plurality of measurement values of the instances of the semiconductor devices, such as the voltages v_sb, v_gb, v_db. In addition, the grid 400 may include a plurality of cuboids 420A, 420B, and 420N which are predetermined regions of the multi-dimensional grid.

In embodiments, for each of the measurement points (e.g., (x,y,z)), a table model for the instance of the semiconductor device can include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the instances of the semiconductor devices. To generate a table entry for a measurement point (x,y,z), for example, a table model tool (e.g., the table model tool 105 in FIG. 1) may determine that the measurement point (x,y,z) is located within the cuboid 420A. This may be represented by the following inequalities:

x_j^l<x<x_j^h,y_j^l<y<y_j^h,z_j^l<z<z_j^h  (1),

where j represents a jth cuboid or the cuboid 420A, l represents a first vertex value of the jth cuboid along a x, y, or z axis, and h represents a second vertex value along the x, y, or z axis.

In accordance with further aspects of the invention, the table model tool can load or retrieve from memory (e.g., the memory 22A and/or the storage system 22B in FIG. 1) a structure of the cuboid 420A. In embodiments, the structure of the cuboid 420A may include vertex values of vertices 425A, 425B, 425C, 425D, 425E, 425F, 425G, and 425H of the cuboid 420A. For example, the vertex 425A may include the vertex values of (x_j^l, y_j^l, z_j^l). Based on the vertex values, the table model tool may determine evaluation values of a Hermite spline function (e.g., a third-order polynomial function) which represents an evaluation function for a semiconductor device (e.g., a function for determining charge of the semiconductor device). For example, an evaluation function g(x,y,z) may be represented by a Hermite spline function f(x,y,z) as follows:

$\begin{array}{cc}g\left(x,y,z\right)\text{~}f\left(x,y,z\right)=\sum _{i=0}^{i<4}\sum _{j=0}^{j<4}\sum _{k=0}^{k<4}C_{\mathrm{ijk}}x^iy^jz^z,& \left(2\right)\end{array}$

where C represents a coefficient (e.g., an evaluation value) of the Hermite spline function f(x,y,z).

In embodiments, the sixty-four (64) coefficients C_ijk of the Hermite spline function f(x,y,z) can be determined based on the vertex values of the cuboid 420A. More specifically, for each of the eight (8) vertices 425A, 425B, 425C, 425D, 425E, 425F, 425G, 425H of the cuboid 420A, the table model tool may determine eight (8) coefficients C of the Hermite spline function f(x,y,z) based on the following equations ((3) to (10)):

For each vertex (x_j^p, y_j^p, z_j^p), where pε[l, h],

C₁=g(x_j^p,y_j^p,z_j^p)  (3);

C₂=dg/dx(x_j^p,y_j^p,z_j^p)  (4);

C₃=dg/dy(x_j^p,y_j^p,z_j^p)  (5);

C₄=dg/dz(x_j^p,y_j^p,z_j^p)  (6);

C₅=dg²/dxdy(x_j^p,y_j^p,z_j^p)  (7);

C₆=dg²/dxdz(x_j^p,y_j^p,z_j^p)  (8);

C₇=dg²/dydz(x_j^p,y_j^p,z_j^p)  (9); and

C₈=dg³/dxdydz(x_j^p,y_j^p,z_j^p)  (10).

In accordance with further aspects of the invention, to determine the higher order derivative values (e.g., dg3/dxdydz(x_j^p, y_j^p, z_j^p)), a perturbed vertex (x_j_hu p−Δx, y_j^p−Δy, z_j^p−Δz) (e.g., a vertex 430) may be used instead of the vertex (x_j^p, y_j^p, z_j^p). Once the coefficients C_ijk of the Hermite spline function f(x,y, z) are determined, the table model tool may store the coefficients C_ijk in memory as the evaluations values in the table entry for the instances of the semiconductor devices. Accordingly, these evaluation values of the table model may be subsequently retrieved and assigned to similar instances of the semiconductor devices, and may be used for semiconductor device evaluation, e.g., to determine currents I_ds and I_db and/or a charge Q_db. For example, during semiconductor device evaluation, a circuit simulator may load or retrieve the stored coefficients C_ijk from memory and/or the table model tool, and based on the coefficients C_ijk, may determine a final value of the Hermite spline function f(x,y,z) that is an approximation of a final value of the evaluation function g(x,y,z), e.g., for determining currents I_ds and I_db and/or a charge Q_db.

Advantageously, since the Hermite spline function f(x,y,z) is determined based on vertex values of cuboids of the grid 400, the Hermite spline function f(x,y,z) and its derivatives ∂f/∂x, ∂f/∂_y, ∂f/∂z are continuous in value across the vertices of the cuboids in the grid 400. In addition, the determination of the Hermite spline function f(x,y,z) requires only known, local vertex values of predetermined cuboids in a grid of a table model. Accordingly, the table model tool may use a smaller grid for a table model, which results in the determination of the Hermite spline function f(x,y,z) having less potential numerical problems like overshooting.

FIG. 5 are exemplary grids 500 of voltages for which a table model of a n-type field effect transistor (nFET) in an inverter is provided and evaluated in accordance with aspects of the invention. The grids 500 include a three-dimensional (3D) view 505 which includes a source-to-bulk voltage v_sb axis, a gate-to-bulk voltage v_gb axis, and a drain-to-bulk voltage v_db axis. The 3D view 505 includes one or more previously-measured measurement points of the nFET in the inverter. For example, each of the measurement points may include a plurality of measurement values of the nFET in the inverter, such as voltages v_sb, v_gb, v_db of the nFET. For each of the measurement points (e.g., (v_sb,v_gb,v_db)), the grids 500 may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the nFET of the inverter that may be retrieved for semiconductor device evaluation.

In embodiments, the grids 500 may further include two-dimensional (2D) views 510, 515, and 520. The 2D view 510 may include an x-y plane (e.g., the source-to-bulk voltage v_sb axis and the gate-to-bulk voltage v_gb) and corresponding measurement points (e.g., (v_sb,v_gb)) in the x-y plane. The 2D view 515 may include an y-z plane (e.g., the drain-to-bulk voltage v_db axis and the gate-to-bulk voltage v_gb) and corresponding measurement points (e.g., (v_db,v_gb)) in the y-z plane. The 2D view 520 may include an x-z plane (e.g., the drain-to-bulk voltage v_db axis and the source-to-bulk voltage v_sb) and corresponding measurement points (e.g., (v_db,v_sb)) in the x-z plane.

FIG. 6 are exemplary grids 600 of voltages for which a table model of the nFET in a plurality of inverters is provided and evaluated in accordance with aspects of the invention The grids 600 include a three-dimensional (3D) view 605 which includes a source-to-bulk voltage v_sb axis, a gate-to-bulk voltage v_gb axis, and a drain-to-bulk voltage v_db axis. The 3D view 605 includes one or more previously-measured measurement points of the nFET in the inverters. For example, each of the measurement points may include a plurality of measurement values of the nFET in the inverters, such as voltages v_sb, v_gb, v_db of the nFET. For each of the measurement points (e.g., (v_sb,v_gb,v_db)), the grids 600 may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the nFET of the inverters that may be retrieved for semiconductor device evaluation.

In embodiments, the grids 600 may further include two-dimensional (2D) views 610, 615, and 620. The 2D view 610 may include an x-y plane (e.g., the source-to-bulk voltage v_sb axis and the gate-to-bulk voltage v_gb) and corresponding measurement points (e.g., (v_sb,v_gb)) in the x-y plane. The 2D view 615 may include an y-z plane (e.g., the drain-to-bulk voltage v_db axis and the gate-to-bulk voltage v_gb) and corresponding measurement points (e.g., (v_db,v_gb)) in the y-z plane. The 2D view 620 may include an x-z plane (e.g., the drain-to-bulk voltage v_db axis and the source-to-bulk voltage v_sb) and corresponding measurement points (e.g., (v_db, v_sb)) in the x-z plane.

FIG. 7 are exemplary grids 700 of voltages for which a table model of the nFET in a plurality of logic gates is provided and evaluated in accordance with aspects of the invention. In embodiments, the logic gates may include inverters, NAND gates, multiplexers, XOR gates, AND-OR-Invert (AOI) gates, and other types of logic gates. The grids 700 include a three-dimensional (3D) view 705 which includes a source-to-bulk voltage v_sb axis, a gate-to-bulk voltage v_gb axis, and a drain-to-bulk voltage v_db axis. The 3D view 705 includes one or more previously-measured measurement points of the nFET in the logic gates. For example, each of the measurement points may include a plurality of measurement values of the nFET in the logic gates, such as voltages v_sb, v_gb, v_db of the nFET. For each of the measurement points (e.g., (v_sb, v_gb, v_db)), the grids 700 may include a corresponding table entry which includes a plurality of generated evaluation values (e.g., coefficients, currents I_ds and I_db, and/or a charge Q_db) of an evaluation function (e.g., a Hermite spline function) for the nFET of the logic gates that may be retrieved for semiconductor device evaluation.

In embodiments, the grids 700 may further include two-dimensional (2D) views 710, 715, and 720. The 2D view 710 may include an x-y plane (e.g., the source-to-bulk voltage v_sb axis and the gate-to-bulk voltage v_gb) and corresponding measurement points (e.g., (v_sb,v_gb)) in the x-y plane. The 2D view 715 may include an y-z plane (e.g., the drain-to-bulk voltage v_db axis and the gate-to-bulk voltage v_gb) and corresponding measurement points (e.g., (v_db,v_gb)) in the y-z plane. The 2D view 720 may include an x-z plane (e.g., the drain-to-bulk voltage v_db axis and the source-to-bulk voltage v_sb) and corresponding measurement points (e.g., (v_db,v_sb)) in the x-z plane.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims, if applicable, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. Accordingly, while the invention has been described in terms of embodiments, those of skill in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.

Claims

1. A method of providing on-demand table models for semiconductor device evaluation, comprising:

measuring one or more measurement values of an instance of a semiconductor device;

providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation; and

generating a table entry in the table model for the one or more measurement values, the table entry comprising one or more evaluation values of an evaluation function for the instance.

2. The method of claim 1, wherein the evaluation function comprises a Hermite spline function.

3. The method of claim 2, wherein the one or more evaluation values comprise a plurality of coefficients of the Hermite spline function that are generated based on the one or more measurement values.

4. The method of claim 3, wherein the plurality of coefficients is generated based on a plurality of vertices of a cuboid of the table model that the one or more measurement values lie within.

5. The method of claim 1, wherein the one or more measurement values comprise at least one of a source-to-bulk voltage, a gate-to-bulk voltage, and a drain-to-bulk voltage.

6. The method of claim 1, wherein the instance comprises a type of the semiconductor device that can be represented by at least one of a model name, a temperature, a corner name, a length, and a width, of the semiconductor device.

7. The method of claim 1, wherein the semiconductor device comprises at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET) of a n-type or a p-type, a n-type field effect transistor (nFET), and a p-type field effect transistor (pFET).

8. The method of claim 1, wherein the providing of the table model comprises retrieving the table model assigned to the instance and comprising a multi-dimensional grid of one or more previously-measured measurement points of the instance.

9. The method of claim 1, wherein the providing of the table model comprises generating the table model comprising a multi-dimensional grid unpopulated with values.

10. A computer program product comprising a tangible computer usable storage medium having readable program code embodied in the tangible computer usable storage medium, the computer program product includes at least one component operable to:

measure one or more measurement values of an instance of a semiconductor device;

provide a table model of the instance for semiconductor device evaluation upon receiving a request for the semiconductor device evaluation; and

generate a table entry in the table model for the one or more measurement values, the table entry comprising one or more evaluation values of an evaluation function for the instance.

11. The computer program product of claim 10, wherein the evaluation function comprises a Hermite spline function.

12. The computer program product of claim 11, wherein the one or more evaluation values comprise a plurality of coefficients of the Hermite spline function that are generated based on the one or more measurement values.

13. The computer program product of claim 12, wherein the plurality of coefficients is generated based on a plurality of vertices of a cuboid of the table model that the one or more measurement values lie within.

14. The computer program product of claim 10, wherein the one or more measurement values comprise at least one of a source-to-bulk voltage, a gate-to-bulk voltage, and a drain-to-bulk voltage.

15. The computer program product of claim 10, wherein the instance comprises a type of the semiconductor device that can be represented by at least one of a model name, a temperature, a corner name, a length, and a width, of the semiconductor device.

16. The computer program product of claim 10, wherein the semiconductor device comprises at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET) of a n-type or a p-type, a n-type field effect transistor (nFET), and a p-type field effect transistor (pFET).

17. The computer program product of claim 10, wherein the providing of the table model comprises retrieving the table model assigned to the instance and comprising a multi-dimensional grid of one or more previously-measured measurement points of the instance.

18. The computer program product of claim 10, wherein the providing of the table model comprises generating the table model comprising a multi-dimensional grid unpopulated with values.

19. A method for semiconductor device evaluation, comprising:

measuring one or more measurement values of an instance of a semiconductor device;

at least one of retrieving and generating, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation based on whether the table model is assigned to the instance; and

generating a table entry in the table model for the one or more measurement values, the table entry comprising a plurality of coefficients of a Hermite spline function for the instance.

20. The method of claim 19, wherein: g  ( x, y, z )  ~  f  ( x, y, z ) = ∑ i = 0 i < 4  ∑ j = 0 j < 4  ∑ k = 0 k < 4  C ijk  x i  y j  z z,

the one or more measurement values lie within a cuboid of the table model; and

the Hermite spline function f(x,y,z) is represented by the following equation:

wherein g(x,y,z) is an evaluation function represented by the Hermite spline function, and C represents the plurality of coefficients of the Hermite spline function.