VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
This is a divisional application of co-pending U.S. patent application Ser. No. 12/556,199 entitled “Varied Silicon Richness Silicon Nitride Formation”, by Yi M A et al., filed Sep. 9, 2009, which is hereby incorporated by reference.
BACKGROUNDConventional computing devices typically include integrated circuit (IC) memory devices. For example, a computing device may be implemented to include volatile IC memory devices, or non-volatile IC memory devices, or both. It is pointed out that one conventional technique utilized for fabricating IC memory devices is the low pressure chemical vapor deposition (LPCVD) technique. However, when the LPCVD technique is utilized to deposit certain materials as part of fabricating IC memory devices, it may exhibit one or more shortcomings.
SUMMARYA method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
In another embodiment, an integrated circuit memory device can include a substrate and a tunnel oxide layer that is disposed over the substrate. Additionally, a first layer of silicon nitride is disposed over the tunnel oxide layer via atomic layer deposition. The first layer of silicon nitride includes a first silicon richness. A second layer of silicon nitride is disposed over the first layer of silicon nitride via atomic layer deposition. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
While particular embodiments in accordance with the invention have been specifically described within this Summary, it is noted that the invention and the claimed subject matter are not limited in any way by these embodiments.
Embodiments of the invention are illustrated by way of example and not by way of limitation in the accompanying drawings and in which like reference numerals refer to similar elements.
The drawings referred to in this description should not be understood as being drawn to scale except if specifically noted.
DETAILED DESCRIPTIONReference will now be made in detail to various embodiments in accordance with the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with various embodiments, it will be understood that these various embodiments are not intended to limit the invention. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as construed according to the Claims. Furthermore, in the following detailed description of various embodiments in accordance with the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be evident to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.
Specifically, in one embodiment, one or more semiconductor wafers 102 can be put into the atomic layer deposition chamber 104 in order to fabricate integrated circuits thereon. It is noted that the one or more semiconductor wafers 102 can be implemented in a wide variety of ways. For example, the one or more semiconductor wafers 102 can be implemented with any semiconductor material, such as but not limited to, silicon crystal. In one embodiment, in order to form one or more varied silicon richness silicon nitride films onto one or more substrates such as semiconductor wafers 102, the atomic layer deposition chamber 104 can be equipped with, but is not limited to, a silane (SiH4) precursor, an ammonia (NH3) precursor, and a silicon precursor that are reactive within the temperature range of approximately 400-900 degrees Celsius (C). In addition, the atomic layer deposition chamber 104 can be further equipped with, but is not limited to, argon (Ar), molecular nitrogen (N2), and a nitrogen precursor. Furthermore, it is pointed out that the atomic layer deposition chamber 104 can be equipped in an embodiment such that the gas flow of each precursor and gas can be independently switched on and off in a matter of seconds, but is not limited to such. After the fabrication process of integrated circuits in accordance with one or more embodiments of the invention, the one or more fabricated wafers 106 that include integrated circuits can be removed from the atomic layer deposition chamber 104. It is pointed out that the fabrication operations of the integrated circuits onto the one or more semiconductor wafers 102 can be completed in-situ.
Next, in one embodiment, the atomic layer deposition chamber 104 can deposit onto (or over or above) the silicon nitride film 206 a silicon nitride film or layer 208 having a different silicon richness than the silicon nitride film 206. It is pointed out that the silicon nitride film 208 can be deposited via atomic layer deposition with any type of silicon richness that is greater than or less than the silicon richness of the previous silicon nitride layer 206. For example in an embodiment, the silicon nitride film or layer 208 can be deposited having a silicon richness of k˜1.4 or ˜1.7, but is not limited to such. Additionally, the silicon nitride film 208 can be deposited to include an upper layer or film of stoichiometric silicon nitride 214, but is not limited to such. Moreover, the silicon nitride film 208 can be deposited at any thickness. For example in an embodiment, the silicon nitride film 208 can be deposited to a thickness of approximately 2-10 angstroms (or approximately 0.2-1 nm), but is not limited to such.
Referring still to
Next, in one embodiment, the atomic layer deposition chamber 104 can deposit onto (or over or above) the silicon nitride film 210 a silicon nitride film or layer 212 having a different silicon richness than the silicon nitride film 210. Note that the silicon nitride film 212 can be deposited via atomic layer deposition with any type of silicon richness that is greater than or less than the silicon richness of the previous silicon nitride layer 210. For example in one embodiment, the silicon nitride film or layer 212 can be deposited having a silicon richness of k˜1 or ˜1.8, but is not limited to such. Additionally, the silicon nitride film 212 can be deposited to include an upper layer or film of stoichiometric silicon nitride 214, but is not limited to such. Moreover, the silicon nitride film 212 can be deposited at any thickness. For example, in an embodiment, the silicon nitride film 212 can be deposited to a thickness of approximately 2-10 angstroms (or approximately 0.2-1 nm), but is not limited to such. In this manner, the integrated circuit memory device 200 can be fabricated utilizing the atomic layer deposition chamber 104 to include varied or variable silicon richness silicon nitride films or layers 206, 208, 210, and 212. It is pointed out that in various embodiments, the integrated circuit memory device 200 can be fabricated in a manner similar to that described with reference to
Referring to
Next, in an embodiment, the atomic layer deposition chamber 104 can deposit onto (or over or above) the silicon nitride film 206′ a silicon nitride film or layer 208′ having a different silicon richness than the silicon nitride film 206′. Note that the silicon nitride film 208′ can be deposited via atomic layer deposition with any type of silicon richness that is greater than or less than the silicon richness of the previous silicon nitride layer 206′. For example in one embodiment, the silicon nitride film or layer 208′ can be deposited having a silicon richness of k˜1.4 or ˜1.8, but is not limited to such. Furthermore, the silicon nitride film 208′ can be deposited at any thickness. For example in an embodiment, the silicon nitride film 208′ can be deposited to a thickness of approximately 2-10 angstroms (or approximately 0.2-1 nm), but is not limited to such.
Referring still to
Next, in one embodiment, the atomic layer deposition chamber 104 can deposit onto (or over or above) the silicon nitride film 210′ a silicon nitride film or layer 212′ having a different silicon richness than the silicon nitride film 210′. It is noted that the silicon nitride film 212′ can be deposited via atomic layer deposition with any type of silicon richness that is greater than or less than the silicon richness of the previous silicon nitride layer 210′. For example in an embodiment, the silicon nitride film or layer 212′ can be deposited having a silicon richness of k˜1 or ˜1.3, but is not limited to such. In addition, the silicon nitride film 212′ can be deposited at any thickness. For example in one embodiment, the silicon nitride film 212′ can be deposited to a thickness of approximately 2-10 angstroms (or approximately 0.2-1 nm), but is not limited to such.
Referring still to
Next, in an embodiment, the atomic layer deposition chamber 104 can deposit onto (or over or above) the silicon nitride film 216 a silicon nitride film or layer 218 having a different silicon richness than the silicon nitride film 216. It is noted that the silicon nitride film 218 can be deposited via atomic layer deposition with any type of silicon richness that is greater than or less than the silicon richness of the previous silicon nitride layer 216. For example in one embodiment, the silicon nitride film or layer 218 can be deposited having a silicon richness of k˜0.8 or ˜1.2, but is not limited to such. Furthermore, the silicon nitride film 218 can be deposited to include an upper layer or film of stoichiometric silicon nitride 214. Moreover, the silicon nitride film 218 can be deposited at any thickness. For example, in an embodiment, the silicon nitride film 218 can be deposited to a thickness of approximately 2-10 angstroms (or approximately 0.2-1 nm), but is not limited to such. In this manner, integrated circuit memory device 220 can be fabricated utilizing the atomic layer deposition chamber 104 to include varied or variable silicon richness silicon nitride films or layers 206′, 208′, 210′, 212′, 216, and 218. It is pointed out that in various embodiments, the integrated circuit memory device 220 can be fabricated in a manner similar to that described with reference to
Referring to
More specifically, in one embodiment, after a semiconductor substrate (e.g., 102) has been put or loaded into an atomic layer deposition chamber (e.g., 104) and a tunnel oxide layer (e.g., 204) has been formed thereon, the chart 300 indicates that the first operation can include injecting the silicon precursor 302 into the chamber for approximately a sixth of the cycle in order to deposit it onto the tunnel oxide layer. Next, the chart 300 indicates that the second operation can include the atomic layer deposition chamber (e.g., 104) performing a molecular nitrogen purge 304 of the chamber for approximately a third of the cycle in order to remove anything remaining from the previous injection of the silicon precursor 302. After that, the chart 300 indicates that the third operation can include injecting the nitrogen precursor 306 into the atomic deposition chamber for approximately a sixth of the cycle in order to deposit it onto the previously deposited silicon precursor 302 and the tunnel oxide layer. Next, the chart 300 indicates that the fourth operation can include the atomic layer deposition chamber (e.g., 104) performing the molecular nitrogen purge 304 of the chamber for approximately a third of the cycle in order to remove anything remaining from the previous injection of the nitrogen precursor 306. It is pointed out that the above described cycle of four operations can be continually repeated in order to deposit a layer of silicon nitride to a desirable thickness that has a desired silicon richness. As such, the chart 300 illustrates one embodiment of an atomic layer deposition process that can be utilized for depositing one or more varied or variable silicon richness silicon nitride layers onto one or more semiconductor wafers.
Specifically, method 400 can include forming a tunnel oxide layer onto (or over or above) one or more semiconductor substrates. Additionally, a desired silicon richness value can be predefined or pre-establish for a first silicon nitride layer to be deposited onto (or over or above) the tunnel oxide layer. Utilizing atomic layer deposition, a first layer of silicon nitride having the desired silicon richness value can be deposited onto (or over or above) the tunnel oxide layer. In addition, a reduction can be made to the silicon richness value. Furthermore, utilizing atomic layer deposition, an additional layer of silicon nitride having the reduced silicon richness value can be deposited onto (or over or above) the previous layer of silicon nitride. A determination can be made as to whether the top layer of silicon nitride is a stoichiometric silicon nitride layer. If not, process 400 can return to the operation involving the reduction of the silicon richness value. However, if it is determined that the top layer of silicon nitride is a stoichiometric silicon nitride layer, process 400 can be ended.
At operation 402 of
At operation 404, a desired silicon richness value can be predefined or pre-establish for a first silicon nitride layer to be deposited onto (or over or above) the tunnel oxide layer. It is noted that the operation 404 can be implemented in a wide variety of ways. For example in one embodiment, at operation 404 a desired silicon richness value can be predefined at a silicon richness ranging from one extreme of almost 100% silicon with the remaining percentage being nitride to the other extreme of almost 100% nitride with the remaining percentage being silicon, and anywhere in between. In addition, in an embodiment, at operation 404 a desired silicon richness value can be predefined at a silicon richness of k˜1.6 (wherein k is the extinction coefficient at a wavelength of 248 nm), but is not limited to such. However, the desired silicon richness value can be predefined at any type of silicon richness at operation 404. It is noted that operation 404 can be implemented in any manner similar to that described herein, but is not limited to such.
At operation 406 of
At operation 408, a reduction can be made to the silicon richness value. It is pointed out that the operation 408 can be implemented in a wide variety of ways. For example in one embodiment, the silicon richness value can be reduced by a predefined amount, but is not limited to such. Additionally, in one embodiment, the silicon richness value can be reduced at operation 408 to have a silicon richness of k˜1.4, but is not limited to such. However, the silicon richness value can be reduced at operation 408 to have any type of silicon richness. Note that operation 408 can be implemented in any manner similar to that described herein, but is not limited to such.
At operation 410 of
At operation 412, a determination can be made as to whether the top layer of silicon nitride is a stoichiometric silicon nitride layer (e.g., as shown by stoichiometric silicon nitride layer 514 of
In accordance with the above description, method 400 can produce integrated circuits (e.g., non-volatile memory devices) that include varied silicon richness silicon nitride layers. It is noted that method 400 may produce one or more potential benefits similar to those described herein, but is not limited to such. In addition, method 400 is not limited in any way by those potential benefits.
Specifically, method 600 can include forming a tunnel oxide layer onto (or over or above) one or more semiconductor substrates. Additionally, using atomic layer deposition, a first layer of silicon nitride having a first silicon richness value can be deposited onto (or over or above) the tunnel oxide layer. Furthermore, utilizing atomic layer deposition, an additional layer of silicon nitride having a different silicon richness value than the previous silicon nitride layer can be deposited onto (or over or above) the previous layer of silicon nitride. A determination can be made as to whether to deposit another silicon nitride layer. If so, process 600 can return to the operation involving the deposition of an additional silicon nitride layer. However, if it is determined that no more silicon nitride layers are to be deposited, process 600 can be ended.
At operation 602 of
At operation 604, using atomic layer deposition, a first layer of silicon nitride (e.g., 206) having a first silicon richness can be deposited onto (or over or above) the tunnel oxide layer. It is noted that the operation 604 can be implemented in a wide variety of ways. For example in one embodiment,
At operation 606 of
At operation 608, a determination can be made as to whether to deposit another silicon nitride layer onto (or over or above) the previous layer of silicon nitride. If so, process 600 can proceed to the beginning of operation 606. However, if it is determined at operation 608 that no more silicon nitride layers are to be deposited, process 600 can be ended. Note that the operation 608 can be implemented in a wide variety of ways. For example, operation 608 can be implemented in any manner similar to that described herein, but is not limited to such.
In accordance with the above description, method 600 can produce integrated circuits (e.g., non-volatile memory devices) that include varied silicon richness silicon nitride layers. Note that method 600 may produce one or more potential benefits similar to those described herein, but is not limited to such. Furthermore, method 600 is not limited in any way by those potential benefits.
The foregoing descriptions of various specific embodiments in accordance with the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The invention is to be construed according to the Claims and their equivalents.
Claims
1. An integrated circuit memory device comprising:
- a substrate;
- a tunnel oxide layer disposed over said substrate;
- a first layer of silicon nitride disposed over said tunnel oxide layer via atomic layer deposition, said first layer of silicon nitride comprises a first silicon richness value; and
- a second layer of silicon nitride disposed over said first layer of silicon nitride via atomic layer deposition, said second layer of silicon nitride comprises a second silicon richness value that is different than said first silicon richness value.
2. The integrated circuit memory device of claim 1, wherein said second silicon richness value is less than said first silicon richness value.
3. The integrated circuit memory device of claim 1, wherein said second silicon richness value is greater than said first silicon richness value.
4. The integrated circuit memory device of claim 1, wherein said substrate comprises silicon.
5. The integrated circuit memory device of claim 1, further comprising:
- a third layer of silicon nitride disposed over said second layer of silicon nitride via atomic layer deposition, said third layer of silicon nitride comprises a third silicon richness value that is different than said second silicon richness value.
6. The integrated circuit memory device of claim 5, wherein said third silicon richness value is less than said second silicon richness value.
7. The integrated circuit memory device of claim 5, wherein said third silicon richness value is greater than said second silicon richness value.
8. The integrated circuit memory device of claim 5, wherein said third layer of silicon nitride comprises a stoichiometric silicon nitride film.
9. An integrated circuit memory device comprising:
- a substrate;
- a tunnel oxide layer disposed over said substrate;
- a first layer of silicon nitride disposed over said tunnel oxide layer via atomic layer deposition, said first layer of silicon nitride comprises a first silicon richness value; and
- a second layer of silicon nitride disposed over said first layer of silicon nitride via atomic layer deposition, said second layer of silicon nitride comprises a second silicon richness value, the first silicon richness value is changed by a predefined amount to produce said second silicon richness value.
10. The integrated circuit memory device of claim 9, wherein said first layer of silicon nitride comprises a non-stoichiometric silicon nitride layer.
11. The integrated circuit memory device of claim 10, wherein said second layer of silicon nitride is in contact with said first layer of silicon nitride.
12. The integrated circuit memory device of claim 9, wherein said second layer of silicon nitride comprises a stoichiometric silicon nitride film.
13. The integrated circuit memory device of claim 9, further comprising:
- a third layer of silicon nitride disposed over said second layer of silicon nitride via atomic layer deposition, said third layer of silicon nitride comprises a third silicon richness value, the second silicon richness value is changed by another predefined amount to produce said third silicon richness value.
14. The integrated circuit memory device of claim 13, wherein said first layer of silicon nitride comprises a non-stoichiometric silicon nitride layer.
15. The integrated circuit memory device of claim 13, wherein said third layer of silicon nitride is in contact with said second layer of silicon nitride.
16. The integrated circuit memory device of claim 13, wherein said third layer of silicon nitride comprises a stoichiometric silicon nitride film.
17. An integrated circuit memory device comprising:
- a substrate;
- a tunnel oxide layer formed on said substrate;
- a first non-stoichiometric silicon nitride layer disposed onto said tunnel oxide layer via a first atomic layer deposition, said a first non-stoichiometric silicon nitride layer comprises a first silicon richness value;
- a first silicon nitride layer disposed above said first non-stoichiometric silicon nitride layer via a second atomic layer deposition, said first silicon nitride layer comprises a second silicon richness value, the first silicon richness value is reduced by a predefined amount to produce said second silicon richness value; and
- a second silicon nitride layer disposed above said first silicon nitride layer via a third atomic layer deposition, said second silicon nitride layer comprises a third silicon richness value, the second silicon richness value is reduced by another predefined amount to produce said third silicon richness value.
18. The integrated circuit memory device of claim 17, wherein said first silicon nitride layer is in contact with said first non-stoichiometric silicon nitride layer.
19. The integrated circuit memory device of claim 17, wherein said second silicon nitride layer is in contact with said first silicon nitride layer.
20. The integrated circuit memory device of claim 17, wherein said second silicon nitride layer comprises an upper film of stoichiometric silicon nitride.
Type: Application
Filed: Mar 23, 2015
Publication Date: Jul 9, 2015
Inventors: Yi MA (Santa Clara, CA), Shenqing FANG (Fremont, CA), Robert OGLE (San Jose, CA)
Application Number: 14/665,311