ERROR CORRECTION AND DECODING
Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.
Various embodiments described herein relate to error correction, and more particularly, to single-bit and multiple-bit error correction.
BACKGROUNDVarious schemes have been devised for error detection and correction in digital apparatus and devices such as memories. In the realm of error correction in memory devices, error detecting and error correcting may be performed separately. For example, schemes such as single error correcting-double error detecting (SEC-DED) have been devised which would allow for the correction of a single-bit error if a double-bit error is detected. In case of multiple-bit errors, however, conventional SEC-DED schemes may not be sufficiently powerful to mitigate these errors.
More powerful error detecting and correcting schemes have been devised to address the problem of multiple-bit errors. For example, schemes such as double error correcting-triple error detecting (DEC-TED) have been devised which would provide more powerful error correcting capabilities than conventional SEC-DED schemes. The area of circuitry typically required for DEC-TED, however, would be much larger than the area required for SEC-DED. Moreover, conventional DEC-TED circuitry typically consumes more power and results in longer latency or time delay than conventional SEC-DED circuitry. For example, when DEC-TED circuitry is utilized to correct a single error, power consumption and time delay would be much greater than SEC-DED circuitry.
Furthermore, pure combinational circuits implementing error correcting codes for single- or multiple-bit error correction may typically consume large amounts of dynamic power when the input changes due to invalid transitions in error location decoding. It would be desirable to reduce the amount of power consumption required for error detection and correction, especially for multiple-bit error detection and correction in low-power integrated circuit devices such as low-power memory chips.
SUMMARYExemplary embodiments of the disclosure are directed to apparatus and methods of double error correction in memories with reduced power consumption.
In an embodiment, an error detection and correction apparatus is provided, the error detection and correction apparatus comprising: a single error location decoder configured to locate single errors in input data; a double error location decoder configured to locate double errors in the input data; and an error corrector coupled to the single error location decoder and the double error location decoder to generate corrected output data.
In another embodiment, an error detection and correction apparatus is provided, the error detection and correction apparatus comprising: means for single error location decoding to locate single errors in input data; means for double error location decoding to locate double errors in the input data; and means for correcting errors to generate corrected output data based on the single errors and the double errors.
In another embodiment, an error detection and correction apparatus is provided, the error detection and correction apparatus comprising: logic configured to locate single errors in input data; logic configured to locate double errors in the input data; and logic configured to generate corrected output data based on the single errors and the double errors.
In yet another embodiment, a memory is provided, the memory comprising: a memory cell; and an error detection and correction apparatus coupled to receive input data from the memory cell and to transmit corrected output data to the memory cell, the error detection and correction apparatus comprising: a single error location decoder configured to locate single errors in input data; a double error location decoder configured to locate double errors in the input data; and an error corrector coupled to the single error location decoder and the double error location decoder to generate corrected output data.
The accompanying drawings are presented to aid in the description of embodiments of the disclosure and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the disclosure are described in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised without departing from the scope of the disclosure. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” does not require that all embodiments include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Moreover, it is understood that the word “or” has the same meaning as the Boolean operator “OR,” that is, it encompasses the possibilities of “either” and “both” and is not limited to “exclusive or” (“XOR”), unless expressly stated otherwise. It is also understood that the symbol “/” between two adjacent words has the same meaning as “or” unless expressly stated otherwise. Moreover, phrases such as “connected to,” “coupled to” or “in communication with” are not limited to direct connections unless expressly stated otherwise.
Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits, for example, central processing units (CPUs), graphic processing units (GPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or various other types of general purpose or special purpose processors or circuits, by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the disclosure may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, “logic configured to” perform the described action.
In an embodiment, the syndrome generator 108 comprises a parity-check matrix decoder, and the error check input (checkbit_in) 104 comprises a parity-check bit input. Such a syndrome generator 108 may be constructed by using one of many known error correcting codes (ECCs). In an embodiment, the parity-check matrix decoder may comprise an XOR-tree based parity-check matrix decoder. For example, the syndrome generator 108 may be constructed by implementing an ECC such as a double error correcting-triple error detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code where a is a primitive element in the Galois field GF(2n):
The syndrome generated by the above parity check matrix may be divided into three parts,
S=v·HT=[v·1,v·H1T,v·H3T]=[S0,S1,S3]
In alternate embodiments, other types of syndrome generators may also be implemented for error detection and correction.
In the embodiment illustrated in
In an embodiment, the controller 110 is implemented to generate the single error correction output (SEC_output) and the double error correction output (DEC_output), which are transmitted to the inputs of a single error correction (SEC) error location decoder 118 and a double error correction (DEC) error location decoder 120, respectively. The SEC error location decoder 118 and the DEC error location decoder 120 will be described in further detail below. In an embodiment, it is desirable to reduce the delay and dynamic power consumption of the error detection and correction apparatus 100 by not having both the SEC error location decoder 118 and the DEC error location decoder 120 actively operating at the same time. For example, if the error in the data input is a single error, then the DEC error location decoder 120 should not be active. Likewise, if the error is a double error, then the SEC error location decoder 118 should not be active.
In an embodiment, the single error correction output (SEC_output) and the double error correction output (DEC_output) of the controller 110 are set to satisfy the above conditions. For example, if the first vector signal output (S0) from the syndrome generator 108 is one, which means that the data input is assumed to have a single error, then the double error correction output (DEC_output) of the controller 110 is a zero vector. In contrast, if the first vector signal output (S0) from the syndrome generator 108 is zero, which means that the data input is assumed to have a double error, then the single error correction output (SEC_output) of the controller is a zero vector.
In an embodiment, the outputs SEC_output and DEC_output of the controller 110 may be generated by the following equations based on the first vector signal output (S0), the second vector signal output (S1) and the third vector signal output (S3) from the syndrome generator 108:
SEC_output=S0*[S1,S3]
DEC_output=(˜S0)*[S1,S3]
where “˜” denotes the logical complement or “NOT.” For the triple error case, S0 is one, which is the same as the single error case.
In the embodiment illustrated in
In an embodiment, the double error detection output (AL_DED) 114 from the double error detector 112 may be generated by the following equation based on the second vector signal output (S1) and the third vector signal output (S3) from the syndrome generator 108:
AL_DED=S13+S3
In a further embodiment, a flag generator 116 is provided in the error detection and correction apparatus 100 as illustrated in
In an embodiment, the error flag (error_flag) 122 may be determined based on the double error detection output (AL_DED) 114 from the double error detector 112 and the first vector signal output (S0) from the syndrome generator 108:
According to the table above, the relationship between the error_flag and S0 can be expressed as follows:
Most significant bit (MSB) of error_flag=AL_DED
Least significant bit (LSB) of error_flag=S0
As described above, the SEC error location decoder 118 is provided to locate single errors and the DEC error location decoder 120 is provided to locate double errors. In an embodiment, the SEC error location decoder 118 is coupled to receive the single error correction output (SEC_output) from the controller 110 and outputs a single error location decoder output (e_sec) 124 based on the SEC_output from the controller 110. In an embodiment, the DEC error location decoder 120 is coupled to receive the double error correction output (DEC_output) from the controller 110 and outputs a double error location decoder output (e_dec) 126 based on the DEC_output from the controller 110.
In an embodiment, a multiplexer 128 is provided in the error detection and correction apparatus 100 to generate a multiplexer output 130. In the embodiment illustrated in
In the embodiment illustrated in
In this embodiment, bit errors up to double errors in the data input may be corrected. Although triple errors may not be correctable in this embodiment, an error flag 122 generated by the flag generator 116 may indicate the presence of a triple error. For example, in the embodiment described with respect to Table 1 above, a two-bit error flag of 11 indicates the presence of a triple error.
In the embodiment described above, the relationships between the number of errors, the first vector signal output (S0) from the syndrome generator 108, the output (e_sec) 124 from the SEC error location decoder 118, the output (e_dec) 126 from the DEC error location decoder 120, the logical complement of AL_DED (˜AL_DED), and the output (e) 130 of the multiplexer 128 are summarized in the following table:
In a further embodiment, an error corrector 134 is provided which has a data input coupled to receive the input data (databit_in), an error vector input coupled to the error vector output (e) 130 of the multiplexer 128, and an output 106 which outputs corrected data (databit_out).
In the embodiment illustrated in
In an embodiment, an error location decoder 228 is provided in the error detection and correction apparatus 200. In an embodiment, the error location decoder 228 has an input coupled to receive the delivered syndrome output 226 from the flip-flop 220, an error location decoder output 230, a single error decoder output (SED) 232 and a double error decoder output (DED) 234. In the embodiment shown in
In an embodiment, the error detection and correction apparatus 200 also includes an error detector 238 which generates a single error detection output (AL_SED) 210 and a triple error detection output (AL_TED) 212. In an embodiment, the error detector 238 has a first input coupled to receive the delivered syndrome output 226 from the flip-flop 220, a second input coupled to receive the single error decoder output (SED) 232, and a third input coupled to receive the double error decoder output (DED) 234 from the error location decoder 228.
In an embodiment, the error detector 238 includes an OR gate 240 having an input coupled to receive the delivered syndrome output 226 and an output configured to output the single error detection output (AL_SED) 210. In a further embodiment, the error detector 238 also includes an AND gate 242 having a first input coupled to the output of the OR gate 240, a second input coupled to the complement of the single error decoder output (SED) 232, and a third output coupled to the complement of the double error decoder output (DED) 234. In the embodiment shown in
In an embodiment, a plurality of logic gates or buffers may be provided in the delay line 300 to delay the propagation of the clock signal 302. In the embodiment shown in
In an embodiment, the delay line 300 and the flip-flop 220 in
In an embodiment, to ensure proper flip-flop operation, the delay line 300 may be designed such that the total time delay produced by the delay line 300 is slighter greater than the maximum time (TI-S) needed for settling the syndromes even though the overall delay of the error detection and correction apparatus 200 is slightly increased. For example, in the embodiment shown in
In an embodiment, the syndrome generator 408 is capable of generating a first vector signal output (S0), a second vector signal output (S1) and a third vector signal output (S3) in response to the data input (databit_in) 402 and the error check input (checkbit_in) 404 in a similar manner to the syndrome generator 108 in the embodiment shown in
In the embodiment illustrated in
In the embodiment illustrated in
In an embodiment, the double error detection output (AL_DED) 414 from the double error detector 412 may be generated by the same equation described above with respect to
AL_DED=S13+S3
In an embodiment, a flag generator 416 is provided in the error detection and correction apparatus 400 as illustrated in
Referring to
In the embodiment shown in
In the embodiment shown in
In an embodiment, the SEC error location decoder 444 and the DEC error location decoder 448 in
In a further embodiment, an error corrector 460 is provided in the error detection and correction apparatus 400 of
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall apparatus. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.
The methods, sequences or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an embodiment of the disclosure can include a computer readable media embodying a method for error detection and correction. Accordingly, the disclosure is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the disclosure.
While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the appended claims. The functions, steps or actions of the method claims in accordance with embodiments described herein need not be performed in any particular order unless expressly stated otherwise. Furthermore, although elements may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Claims
1. An error detection and correction apparatus, comprising:
- a single error location decoder configured to locate single errors in input data;
- a double error location decoder configured to locate double errors in the input data; and
- an error corrector coupled to the single error location decoder and the double error location decoder to generate corrected output data.
2. The apparatus of claim 1, further comprising:
- a syndrome generator configured to receive the input data and to generate a first vector signal output and one or more additional vector signal outputs based on the input data; and
- a controller configured to receive the first vector signal output and the one or more additional vector signal outputs, and to generate a single error correction output and a double error correction output based on the first vector signal output and the one or more additional vector signal outputs,
- wherein the single error location decoder is configured to receive the single error correction output and to generate a single error location decoder output; and
- wherein the double error location decoder is configured to receive the double error correction output and to output a double error location decoder output.
3. The apparatus of claim 2, wherein the syndrome generator comprises a parity-check matrix decoder.
4. The apparatus of claim 3, wherein the parity-check matrix decoder comprises an XOR-tree based parity-check matrix decoder.
5. The apparatus of claim 2, further comprising a double error detector configured to receive the first vector signal output and the one or more additional vector signal outputs from the syndrome generator.
6. The apparatus of claim 5, wherein the double error detector is configured to generate a double error detection output based on two or more of the first vector signal output and the one or more additional vector signal outputs.
7. The apparatus of claim 6, further comprising a flag generator configured to receive the double error detection output from the double error detector and the first vector signal output from the syndrome generator, and to generate an error flag based on the double error detection output and the first vector signal output.
8. The apparatus of claim 6, further comprising a multiplexer, comprising:
- a first input coupled to the single error location decoder output; and
- a second input coupled to the double error location decoder output.
9. The apparatus of claim 8, wherein the multiplexer further comprises:
- a control input configured to receive the double error detection output; and
- an output configured to output either the single error location decoder output or the double error location decoder output based on the control input.
10. The apparatus of claim 9, further comprising an error corrector, comprising:
- an input configured to receive the input data;
- an error location decoder input coupled to the output of the multiplexer; and
- an output configured to output the corrected output data based on the input data and the error location decoder input.
11. The apparatus of claim 2, further comprising:
- a timing controller having a control input and a control output;
- a first flip-flop comprising an input coupled to receive the single error correction output, a toggle input coupled to the control output of the timing controller, and an output configured to output a first delivered syndrome output; and
- a second flip-flop comprising an input coupled to receive the double error correction output, a toggle input coupled to the control output of the timing controller, and an output configured to output a second delivered syndrome output.
12. The apparatus of claim 11, wherein the timing controller comprises a delay unit.
13. The apparatus of claim 12, wherein the delay unit comprises one or more logic gates.
14. The apparatus of claim 13, wherein the delay unit further comprises one or more buffers.
15. The apparatus of claim 10, wherein the first flip-flop comprises a first positive edge triggered flip-flop, and wherein the second flip-flop comprises a second positive edge triggered flip-flop.
16. An error detection and correction apparatus, comprising:
- means for single error location decoding to locate single errors in input data;
- means for double error location decoding to locate double errors in the input data; and
- means for correcting errors to generate corrected output data based on the single errors and the double errors.
17. The apparatus of claim 16, further comprising:
- means for generating a syndrome, wherein the means for generating the syndrome is configured to receive the input data and to output a first vector signal output and one or more additional vector signal outputs based on the input data; and
- means for generating a single error correction output and a double error correction output, wherein the means for generating the single error correction output and the double error correction output is configured to receive the first vector signal output and the one or more additional vector signal outputs, and to generate a single error correction output and a double error correction output based on the first vector signal output and the one or more additional vector signal outputs,
- wherein the means for single error location decoding is configured to receive the single error correction output and to output a single error location decoder output; and
- wherein the means for double error location decoding is configured to receive the double error correction output and to output a double error location decoder output.
18. The apparatus of claim 17, wherein means for generating the syndrome comprises a parity-check matrix decoder.
19. The apparatus of claim 17, further comprising means for detecting double errors based on the first vector signal output and the one or more additional vector signal outputs to generate a double error detection output.
20. The apparatus of claim 19, further comprising means for generating an error flag based on the double error detection output and the first vector signal output.
21. The apparatus of claim 20, further comprising means for multiplexing, comprising:
- a first input coupled to the single error location decoder output;
- a second input coupled to the double error location decoder output;
- a control input configured to receive the double error detection output; and
- an output configured to output either the single error location decoder output or the double error location decoder output based on the control input.
22. The apparatus of claim 21, further comprising means for correcting errors, comprising:
- a data input configured to receive the input data;
- an error location decoder input coupled to the output of the means for multiplexing; and
- an output configured to output corrected data based on the data input and the error location decoder input.
23. The apparatus of claim 17, further comprising:
- means for controlling timing, the means for controlling timing having a control input and a control output;
- a first flip-flop comprising an input coupled to receive the single error correction output, a toggle input coupled to the control output of the means for controlling timing, and an output configured to output a first delivered syndrome output; and
- a second flip-flop comprising an input coupled to receive the double error correction output, a toggle input coupled to the control output of the means for controlling timing, and an output configured to output a second delivered syndrome output.
24. The apparatus of claim 23, wherein the first delivered syndrome output is delivered to the means for single error location decoding, and wherein the second delivered syndrome output is delivered to the means for double error location decoding.
25. An error detection and correction apparatus, comprising:
- logic configured to locate single errors in input data;
- logic configured to locate double errors in the input data; and
- logic configured to generate corrected output data based on the single errors and the double errors.
26. The apparatus of claim 25, further comprising:
- logic configured to generate a syndrome, wherein the logic configured to generate the syndrome is configured to receive the input data and to output a first vector signal output and one or more additional vector signal outputs based on the input data; and
- logic configured to generate a single error correction output and a double error correction output based on the first vector signal output and the one or more additional vector signal outputs,
- wherein the logic configured to locate single errors is configured to receive the single error correction output and to output a single error location decoder output; and
- wherein the logic configured to locate double errors is configured to receive the double error correction output and to output a double error location decoder output.
27. The apparatus of claim 26, further comprising:
- logic configured to control timing;
- a first flip-flop comprising an input coupled to receive the single error correction output, a toggle input coupled to the logic configured to control timing, and an output configured to output a first delivered syndrome output; and
- a second flip-flop comprising an input coupled to receive the double error correction output, a toggle input coupled to the logic configured to control timing, and an output configured to output a second delivered syndrome output.
28. A memory, comprising:
- a memory cell; and
- an error detection and correction apparatus coupled to receive input data from the memory cell and to transmit corrected output data to the memory cell, the error detection and correction apparatus comprising: a single error location decoder configured to locate single errors in input data; a double error location decoder configured to locate double errors in the input data; and an error corrector coupled to the single error location decoder and the double error location decoder to generate corrected output data.
29. The memory of claim 28, wherein the error detection and correction apparatus further comprises:
- a syndrome generator configured to receive the input data and to generate a first vector signal output and one or more additional vector signal outputs based on the input data; and
- a controller configured to receive the first vector signal output and the one or more additional vector signal outputs, and to generate a single error correction output and a double error correction output based on the first vector signal output and the one or more additional vector signal outputs,
- wherein the single error location decoder is configured to receive the single error correction output and to generate a single error location decoder output; and
- wherein the double error location decoder is configured to receive the double error correction output and to output a double error location decoder output.
30. The memory of claim 29, wherein the error detection and correction apparatus further comprises:
- a timing controller having a control input and a control output;
- a first flip-flop comprising an input coupled to receive the single error correction output, a toggle input coupled to the control output of the timing controller, and an output configured to output a first delivered syndrome output; and
- a second flip-flop comprising an input coupled to receive the double error correction output, a toggle input coupled to the control output of the timing controller, and an output configured to output a second delivered syndrome output.
Type: Application
Filed: Sep 14, 2015
Publication Date: Mar 16, 2017
Patent Grant number: 9800271
Inventors: Seong-Ook JUNG (Seoul), Sara CHOI (Seoul), Byungkyu SONG (Seoul), Taehui NA (Seoul), Jisu KIM (Seoul), Jung Pill KIM (San Diego, CA), Sungryul KIM (San Diego, CA), Taehyun KIM (Cupertino, CA), Seung Hyuk KANG (San Diego, CA)
Application Number: 14/852,988