APPARATUS AND METHOD FOR APPLYING DYNAMIC COMPENSATION TO FEEDBACK SIGNAL GENERATED FROM LOADLINE OF VOLTAGE REGULATOR
A feedback loop circuit of a voltage regulator includes a loadline and a compensation circuit. The loadline generates a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and outputs the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit generates a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.
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This application claims the benefit of U.S. Provisional Application No. 63/195,733, filed on Jun. 2, 2021. The content of the application is incorporated herein by reference.
BACKGROUNDThe present invention relates to a voltage regulator design, and more particularly, to a voltage regulator using a compensation circuit to apply dynamic compensation to a feedback signal generated from a loadline and an associated compensation method.
In an electronic device, a voltage regulator is used to supply stable power to electronic loads. The voltage regulator is typically designed to maintain an output voltage within specified limits. In some applications, the voltage regulator may support an adaptive voltage positioning (AVP) feature. Hence, a loadline is implemented for generating a feedback signal according to a load current supplied to a load. For example, the load may be a microprocessor. However, sensing the load current is not feasible. To obtain the load information, inductor current is often sensed and used as an approximation of the load current. In some cases, this approximation fails and affects the performance of the output voltage regulation. Thus, there is a need for an innovative compensation design for a voltage regulator with AVP.
SUMMARYOne of the objectives of the claimed invention is to provide a voltage regulator using a compensation circuit to apply dynamic compensation to a feedback signal generated from a loadline and an associated compensation method.
According to a first aspect of the present invention, an exemplary feedback loop circuit of a voltage regulator is disclosed. The exemplary feedback loop circuit includes a loadline and a compensation circuit. The loadline is arranged to generate a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and output the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit is arranged to generate a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.
According to a second aspect of the present invention, an exemplary compensation method employed by a voltage regulator is disclosed. The exemplary compensation method includes: according to a sensed current signal that provides information of an inductor current of the voltage regulator, generating a feedback signal through a loadline; generating a compensation signal to compensate for a deviation of an output voltage of the voltage regulation, wherein the feedback signal is affected by the compensation signal; and outputting the feedback signal to a controller circuit of the voltage regulator for regulating the output voltage.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
As shown in
However, the above-mentioned approximation fails under some cases. If no compensation is applied to the inaccurate loadline, the performance of the PWM controller will be degraded.
Furthermore, during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens. For example, the output voltage undershoot happens when there is transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).
Regarding a voltage regulator with AVP, the output voltage is affected when the inductor current cannot be an approximation of the load current. Specifically, as long as the inductor current undergoes some kind of dynamic, it affects the output voltage, even the load current is unchanged. To address this issue, the present invention proposes using the compensation circuit 110 to generate a compensation signal Sc to compensate for a deviation (e.g. offset or undershoot) of the output voltage Vo. The feedback signal Sfb generated from the loadline 108 is affected by the compensation signal Sc. In other words, the feedback signal Sfb is compensated before arriving at the controller circuit 102. For example, the compensation signal Sc may be injected to the feedback signal Sfb to update the feedback signal Sfb finally obtained by the controller circuit 102, that is, Sfb=Sfb+Sc. The polarity of the compensation signal Sc may vary, depending upon the disturbance of the inductor current IL. The compensation circuit 110 may receive a plurality of parameters PR1-PRM (M≥2), and may refer to one or more of the parameters PR1-PRM to determine polarity and/or magnitude of the compensation signal Sc. Further details of the compensation circuit 110 are described as below with reference to the accompanying drawings.
The feedback loop circuit 406 includes a loadline 408 and a compensation circuit 410. The feedback signal Sfb generated from the loadline 408 is based on the sensed current signal Isen that provides information of the inductor current IL. It should be noted that the present invention has no limitations on the means of generating the sensed current signal Isen that is representative of the inductor current IL. The compensation circuit 110 shown in
Please refer to
A DVID down event is triggered at t3, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t3 to a lower voltage setting at t4 according to a slew rate SR_DN determined by the load 101 (e.g. microprocessor). During the DVID down event, the inductor current IL is decreased by the discharging current Ic of the output capacitor Co. In response to the DVID down event, the compensation current Icomp is generated by the compensation circuit 410 according to the output capacitance Co and the slew rate SR=SR_DN. During the DVID down event, the disturbance ΔI2 of the inductor current IL is compensated by the compensation current Icomp. In this way, the final feedback signal Sfb (Sfb=Sfb+Sc) received by the controller circuit 402 remains unchanged under a condition that the load current Io is unchanged during the period from t3 to t4.
In this embodiment, the voltage regulator 600 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit 402 and the load 101 in parallel. The parameter PHN includes information of a phase change event. For example, the parameter PHN may indicate whether a phase change event happens, and may further indicate that the phase change event changes the number of phases enabled in the voltage regulator 600 from a present phase number to a next phase number (which may be larger than or smaller than the present phase number). In this embodiment, the compensation circuit 610 is arranged to generate the compensation signal Sc in response to a phase number change event. For example, the compensation circuit 610 may set the compensation current Icomp according to a difference between the present phase number and the next phase number.
The parameter Trig indicates whether triggering of PWM pulse happens. For example, a control voltage Vc fed into a PWM signal generator circuit 604 is derived from an output signal of a filter circuit 602, and triggering of PWM pulse happens each time the waveform of the control voltage Vc crosses over the waveform of the inductor current IL. In some embodiments of the present invention, the compensation circuit 610 may further refer to the parameter Trig to control the timing (e.g. start time and duration) of generating the compensation signal Sc since the phase number change event. Hence, the compensation circuit 610 may not start generating the compensation signal Sc at the time the phase number change event happens.
The parameter DCM indicates whether an operation mode transition event happens. For example, the operation mode transition event may include transition between CCM and DCM. For another example, the operation mode transition event may include transition between different operation modes supported by the voltage regulator 600. In this embodiment, the compensation circuit 610 is further arranged to generate the compensation signal Sc in response to the operation mode transition event (e.g. DCM/CCM transition event). Furthermore, the compensation circuit 610 may further refer to the parameter Trig to control the timing (e.g. start time and duration) of generating the compensation signal Sc since the operation mode transition event (e.g. DCM/CCM transition event). Hence, the compensation circuit 610 may not start generating the compensation signal Sc at the time the operation mode transition event (e.g. DCM/CCM transition event) happens.
As mentioned above, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo. Furthermore, the output voltage undershoot may happen when an operation mode transition event (e.g. CCM/DCM transition event) happens. The compensation signal Sc is derived from the compensation current Icomp. Since the compensation current Icomp is generated in response to the phase number change event or the operation mode transition event, and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL), disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the phase number change event or the operation mode transition event) and the load current IL (which may be increased during the phase number change event or the operation mode transition event) can be compensated by the compensation signal Sc.
Regarding the embodiment shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A feedback loop circuit of a voltage regulator comprising:
- a loadline, arranged to generate a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and output the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator; and
- a compensation circuit, arranged to generate a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.
2. The feedback loop circuit of claim 1, wherein the compensation circuit is arranged to inject the compensation signal to the feedback signal.
3. The feedback loop circuit of claim 2, wherein the compensation circuit comprises:
- a compensation current generator circuit, arranged to generate a compensation current; and
- a filter circuit, arranged to apply filtering to the compensation current to generate the compensation signal.
4. The feedback loop circuit of claim 1, wherein the compensation circuit is arranged to generate the compensation signal in response to a specific event that leads to the deviation of the output voltage.
5. The feedback loop circuit of claim 4, wherein the compensation circuit is arranged to generate the compensation signal during a period in which a load current supplied from the voltage regulator to a load is unchanged.
6. The feedback loop circuit of claim 4, wherein the specific event is a dynamic voltage identification (DVID) event.
7. The feedback loop circuit of claim 6, wherein the DVID event changes the output voltage from a first voltage setting to a second voltage setting, and the compensation circuit is arranged to determine the compensation signal according to capacitance of an output capacitor of the voltage regulator and a slew rate of changing the output voltage from the first voltage setting to the second voltage setting.
8. The feedback loop circuit of claim 4, wherein the voltage regulator is a multi-phase voltage regulator, and the specific event is a phase number change event.
9. The feedback loop circuit of claim 8, wherein the phase number change event changes a number of phases enabled in the voltage regulator from a first phase number to a second phase number, and the compensation circuit is arranged to set the compensation signal according to a difference between the first phase number and the second phase number.
10. The feedback loop circuit of claim 8, wherein the compensation circuit is arranged to control timing of generating the compensation signal according to triggering of pulse-width modulation (PWM) pulse since the phase number change event.
11. The feedback loop circuit of claim 4, wherein the specific event is an operation mode transition event.
12. The feedback loop circuit of claim 11, wherein the operation mode transition event comprises transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).
13. The feedback loop circuit of claim 11, wherein the compensation circuit is arranged to control timing of generating the compensation signal according to triggering of pulse-width modulation (PWM) pulse since the operation mode transition event.
14. A compensation method employed by a voltage regulator comprising:
- according to a sensed current signal that provides information of an inductor current of the voltage regulator, generating a feedback signal through a loadline;
- generating a compensation signal to compensate for a deviation of an output voltage of the voltage regulation, wherein the feedback signal is affected by the compensation signal; and
- outputting the feedback signal to a controller circuit of the voltage regulator for regulating the output voltage.
15. The compensation method of claim 14, wherein the compensation signal is injected to the feedback signal.
16. The compensation method of claim 14, wherein generating the compensation signal to compensate for the deviation of the output voltage comprises:
- generating the compensation signal in response to a specific event that leads to the deviation of the output voltage.
17. The compensation method of claim 16, wherein the specific event is a dynamic voltage identification (DVID) event.
18. The compensation method of claim 16, wherein the voltage regulator is a multi-phase voltage regulator, and the specific event is a phase number change event.
19. The compensation method of claim 16, wherein the specific event is an operation mode transition event.
20. The compensation method of claim 19, wherein the operation mode transition event comprises transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).
Type: Application
Filed: Apr 13, 2022
Publication Date: Dec 8, 2022
Applicant: MediaTek Singapore Pte. Ltd. (Singapore)
Inventors: Man Pun Chan (San Jose, CA), Hao-Ping Hong (San Jose, CA), Yung-Chih Yen (San Jose, CA), Chien-Hui Wang (Hsinchu), Cheng-Hsuan Fan (Hsinchu), Jian-Rong Huang (Hsinchu)
Application Number: 17/719,401