MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION
Memory array structures might include a first data line selectively connected to a first plurality of memory cells, a second data line selectively connected to a second plurality of memory cells, a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line, a second dielectric containing a void extending between a second portion of the first data line and a second portion of the second data line, and a top contact overlying and in contact with the first portion of the first data line.
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This application claims the benefit of U.S. Provisional Application No. 63/402,488, filed on Aug. 31, 2022, hereby incorporated herein in its entirety by reference.
TECHNICAL FIELDThe present disclosure relates generally to integrated circuits, and, in particular, in one or more embodiments, the present disclosure relates to memory array structures and methods of their fabrication, as well as apparatus containing such memory array structures.
BACKGROUNDMemories (e.g., memory devices) are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor might be connected to a source, while each drain select transistor might be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.
In programming memory, memory cells might be programmed as what are often termed single-level cells (SLC). SLC might use a single memory cell to represent one digit (e.g., one bit) of data. For example, in SLC, a Vt of 2.5V or higher might indicate a programmed memory cell (e.g., representing a logical 0) while a Vt of −0.5V or lower might indicate an erased memory cell (e.g., representing a logical 1). Such memory might achieve higher levels of storage capacity by including multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., or combinations thereof in which the memory cell has multiple levels that enable more digits of data to be stored in each memory cell. For example, MLC might be configured to store two digits of data per memory cell represented by four Vt ranges, TLC might be configured to store three digits of data per memory cell represented by eight Vt ranges, QLC might be configured to store four digits of data per memory cell represented by sixteen Vt ranges, and so on.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments might be utilized and structural, logical and electrical changes might be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.
The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps might have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.
The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting by an electrically conductive path unless otherwise apparent from the context.
It is recognized herein that even where values might be intended to be equal, variabilities and accuracies of industrial processing and operation might lead to differences from their intended values. These variabilities and accuracies will generally be dependent upon the technology utilized in fabrication and operation of the integrated circuit device. As such, if values are intended to be equal, those values are deemed to be equal regardless of their resulting values.
Memory device 100 includes an array of memory cells 104 that might be logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown in
A row decode circuitry 108 and a column decode circuitry 110 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104. Memory device 100 also includes input/output (I/O) control circuitry 112 to manage input of commands, addresses and data to the memory device 100 as well as output of data and status information from the memory device 100. An address register 114 is in communication with I/O control circuitry 112 and row decode circuitry 108 and column decode circuitry 110 to latch the address signals prior to decoding. A command register 124 is in communication with I/O control circuitry 112 and control logic 116 to latch incoming commands.
A controller (e.g., the control logic 116 internal to the memory device 100) controls access to the array of memory cells 104 in response to the commands and might generate status information for the external processor 130, i.e., control logic 116 is configured to perform array operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells 104. The control logic 116 is in communication with row decode circuitry 108 and column decode circuitry 110 to control the row decode circuitry 108 and column decode circuitry 110 in response to the addresses. The control logic 116 might include instruction registers 128 which might represent computer-usable memory for storing computer-readable instructions. For some embodiments, the instruction registers 128 might represent firmware. Alternatively, the instruction registers 128 might represent a grouping of memory cells, e.g., reserved block(s) of memory cells, of the array of memory cells 104.
Control logic 116 might also be in communication with a cache register 118. Cache register 118 latches data, either incoming or outgoing, as directed by control logic 116 to temporarily store data while the array of memory cells 104 is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data might be passed from the cache register 118 to the data register 120 for transfer to the array of memory cells 104, then new data might be latched in the cache register 118 from the I/O control circuitry 112. During a read operation, data might be passed from the cache register 118 to the I/O control circuitry 112 for output to the external processor 130, then new data might be passed from the data register 120 to the cache register 118. The cache register 118 and/or the data register 120 might form (e.g., might form a portion of) a page buffer of the memory device 100. A data register 120 might further include sense circuits (not shown in
Memory device 100 receives control signals at control logic 116 from processor 130 over a control link 132. The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) might be further received over control link 132 depending upon the nature of the memory device 100. Memory device 100 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor 130 over a multiplexed input/output (I/O) bus 134 and outputs data to processor 130 over I/O bus 134.
For example, the commands might be received over input/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry 112 and might then be written into command register 124. The addresses might be received over input/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry 112 and might then be written into address register 114. The data might be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and then might be written into cache register 118. The data might be subsequently written into data register 120 for programming the array of memory cells 104. For another embodiment, cache register 118 might be omitted, and the data might be written directly into data register 120. Data might also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference might be made to I/O pins, they might include any conductive nodes providing for electrical connection to the memory device 100 by an external device (e.g., processor 130), such as conductive pads or conductive bumps as are commonly used.
It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device 100 of
Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) might be used in the various embodiments.
Memory array 200A might be arranged in rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column might include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings 2060 to 206M. Each NAND string 206 might be connected (e.g., selectively connected) to a common source (SRC) 216 and might include memory cells 2080 to 208N. The memory cells 208 might represent non-volatile memory cells for storage of data. The memory cells 2080 to 208N might include memory cells intended for storage of data, and might further include other memory cells not intended for storage of data, e.g., dummy memory cells. Dummy memory cells are typically not accessible to a user of the memory, and are instead typically incorporated into the string of series-connected memory cells for operational advantages that are well understood.
The memory cells 208 of each NAND string 206 might be connected in series between a select gate 210 (e.g., a field-effect transistor), such as one of the select gates 2100 to 210M (e.g., that might be source select transistors, commonly referred to as select gate source), and a select gate 212 (e.g., a field-effect transistor), such as one of the select gates 2120 to 212M (e.g., that might be drain select transistors, commonly referred to as select gate drain). Select gates 2100 to 210M might be commonly connected to a select line 214, such as a source select line (SGS), and select gates 2120 to 212M might be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates 210 and 212 might utilize a structure similar to (e.g., the same as) the memory cells 208. The select gates 210 and 212 might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.
A source of each select gate 210 might be connected to common source 216. The drain of each select gate 210 might be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 might be connected to memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 might be configured to selectively connect a corresponding NAND string 206 to common source 216. A control gate of each select gate 210 might be connected to select line 214.
The drain of each select gate 212 might be connected to the data line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 might be connected to the data line 2040 for the corresponding NAND string 2060. The source of each select gate 212 might be connected to a memory cell 208N of the corresponding NAND string 206. For example, the source of select gate 2120 might be connected to memory cell 208N of the corresponding NAND string 2060. Therefore, each select gate 212 might be configured to selectively connect a corresponding NAND string 206 to the corresponding data line 204. A control gate of each select gate 212 might be connected to select line 215.
The memory array in
Typical construction of memory cells 208 includes a data-storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate 236, as shown in
A column of the memory cells 208 might be a NAND string 206 or a plurality of NAND strings 206 selectively connected to a given data line 204. A row of the memory cells 208 might be memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 can, but need not, include all memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 might often be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often include every other memory cell 208 commonly connected to a given access line 202. For example, memory cells 208 commonly connected to access line 202N and selectively connected to even data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) might be one physical page of memory cells 208 (e.g., even memory cells) while memory cells 208 commonly connected to access line 202N and selectively connected to odd data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) might be another physical page of memory cells 208 (e.g., odd memory cells). Although data lines 2043-2045 are not explicitly depicted in
Although the example of
The three-dimensional NAND memory array 200B might be formed over peripheral circuitry 226. The peripheral circuitry 226 might represent a variety of circuitry for accessing the memory array 200B. The peripheral circuitry 226 might include complementary circuit elements. For example, the peripheral circuitry 226 might include both n-channel region and p-channel region transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience.
The data lines 2040-204M might be connected (e.g., selectively connected) to a buffer portion 240, which might be a portion of a page buffer of the memory. The buffer portion 240 might correspond to a memory plane (e.g., the set of blocks of memory cells 2500-250L). The buffer portion 240 might include sense circuits (not shown in
As noted, memory cells and select gates might utilize a same structure, e.g., the structure of a programmable field-effect transistor (FET). These transistors might be formed from alternating layers of conductive materials and dielectric materials, formed around a pillar that acts as a common channel for the transistors, and which might be hollow.
In
Each instance of control gate 352 might be formed of one or more conductive materials. A control gate 352 might comprise, consist of, or consist essentially of conductively doped polysilicon. Alternatively or in addition, each control gate 352 might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material.
Each instance of dielectric 358 might be formed of one or more dielectric materials. A dielectric 358 might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiO2), and/or may comprise, consist of, or consist essentially of a high-K dielectric material, such as aluminum oxides (AlOx), hafnium oxides (HfOx), hafnium aluminum oxides (HfAlOx), hafnium silicon oxides (HfSiOx), lanthanum oxides (LaOx), tantalum oxides (TaOx), zirconium oxides (ZrOx), zirconium aluminum oxides (ZrAlOx), or yttrium oxide (Y2O3), as well as any other dielectric material. High-K dielectrics as used herein means a material having a dielectric constant greater than that of silicon dioxide. A dielectric 358 might further comprise, consist of, or consist essentially of a spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or a high-density-plasma (HDP) oxide. As one example, the dielectric 560 might contain silicon dioxide.
As depicted in
The charge-blocking material 360 might function as a charge-blocking node for future memory cells and other transistors having a same structure, and might include one or more dielectric materials, such as described with reference to the instances of dielectric 358. For example, the charge-blocking material 360 might include a high-K dielectric material. The charge-storage material 362 might function as a charge-storage node for future memory cells and other transistors having a same structure, and might include one or more conductive and/or dielectric materials capable of storing a charge. For example, the charge-storage material 362 might include polysilicon, which might be conductively doped. Alternatively, the charge-storage material 362 might include silicon nitride. The dielectric 364 might function as a gate dielectric for future memory cells and other transistors having a same structure, and might include one or more dielectric materials such as described with reference to the instances of dielectric 358. For example, the dielectric 364 might include silicon dioxide. The channel material 366 might function as a channel for future memory cells and other transistors having a same structure, and might include one or more semiconductor materials, which might be conductively doped to provide desired threshold voltage characteristics.
A contact (e.g., contact plug) 370 might be formed in a dielectric 372, and might be overlying and in physical contact with the channel material structure 354, and in electrical contact with its channel material 366. The contact 370 might contain one or more conductive materials, such as described with reference to the control gates 352. As one example, the contact 370 might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. The dielectric 372 might contain one or more dielectric materials, such as described with reference to the dielectric 358. As one example, the dielectric 372 might comprise, consist of, or consist essentially of silicon dioxide.
A contact (e.g., contact via) 374 might be formed in a dielectric 376, and might be overlying and in electrical contact with the contact 370. The contact 374 might further be in physical contact with the contact 370. The contact 374 might contain one or more conductive materials, such as described with reference to the control gates 352. As one example, the contact 374 might comprise, consist of, or consist essentially of a conductively-doped semiconductor material, such as conductively-doped polysilicon. For example, the contact 370 and the contact 374 might both contain conductively-doped polysilicon of a same conductivity type. Alternatively or in addition, the contact 374 might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium(V) and zirconium (Zr) are generally recognized as refractory metals. The dielectric 376 might contain one or more dielectric materials, such as described with reference to the dielectric 358. As one example, the dielectric 376 might comprise, consist of, or consist essentially of silicon dioxide.
A data line 204 might be formed to be overlying and in electrical contact with the contact 374. The data line 204 might further be in physical contact with the contact 374. The data line 204 might contain one or more conductive materials, such as described with reference to the control gates 352. As one example, the data line 204 might comprise, consist of, or consist essentially of a refractory metal, such as tungsten. A dielectric cap 378 might be formed to be overlying the data line 204. The dielectric cap 378 might contain one or more dielectric materials, such as described with reference to the dielectric 358. As one example, the dielectric cap 378 might comprise, consist of, or consist essentially of a dielectric nitride, such as silicon nitride or carbon nitride. In general, the dielectric material of the dielectric cap 378 should be different than the dielectric material of the dielectric 376 to allow for removal of a portion of the dielectric cap 378 without removal of undesirable amounts of the dielectric 376.
A top contact 380 might be formed in a dielectric 382 to be overlying and in electrical contact with the data line 204. The top contact 380 might further be in physical contact with the data line 204. The top contact 380 might contain one or more conductive materials, such as described with reference to the control gates 352. As one example, the top contact 380 might comprise, consist of, or consist essentially of a refractory metal, such as tungsten. The dielectric 382 might contain one or more dielectric materials of low conformability. For example, the dielectric 382 might comprise, consist of, or consist essentially of a dielectric material of low conformability such as tetraethylorthosilicate (TEOS) or silane oxide. A dielectric material will be deemed to be of low conformability if, as will be described infra, it is expected to form voids between adjacent data lines 204 during formation of the dielectric 382 overlying the data lines 204, and is not expected to conform sufficiently to fill spaces between those adjacent data lines 204.
In
In
In
Instances of data lines 204, e.g., data lines 2041-2045 as depicted, might be overlying respective fins 390 of the dielectric 376. Instances of dielectric caps 378, e.g., dielectric caps 3780-3786, might be overlying respective data lines 204, e.g., data lines 2040-2046. Although data lines 2040 and 2046 are not explicitly depicted in
In
Each opening 394 might expose portions of corresponding dielectric caps 378. For example, opening 3941 might expose respective portions of dielectric caps 3780, 3781 and 3782; opening 3942 might expose respective portions of dielectric caps 3781, 3782 and 3783; opening 3943 might expose respective portions of dielectric caps 3782, 3783 and 3784; opening 3944 might expose respective portions of dielectric caps 3783, 3784 and 3785; and opening 3945 might expose respective portions of dielectric caps 3784, 3785 and 3786. The openings 394 might further expose portions of data lines 204 corresponding to their respective portions of dielectric caps 378, and portions of the dielectric 376 between their respective portions of dielectric caps 378. While each opening 394 is depicted to expose a full width of one dielectric cap 378, and partial widths for adjacent dielectric caps 378, the openings could be larger, e.g., exposing full widths of the adjacent dielectric caps 378 or exposing additional dielectric caps 378. For example, opening 3943 is depicted to expose a full width of dielectric cap 3783 and partial widths of dielectric caps 3782 and 3784. Optionally, opening 3943 could be expanded to expose full widths of dielectric caps 3782 and 3784, and could be further expanded to expose partial or full widths of next adjacent dielectric caps 3781 and/or 3785, and so on. For embodiments including a dielectric liner 377, the dielectric caps 378, data lines 204 and dielectric 376 will be deemed to be exposed by an opening 394 if there is no overlying sacrificial material 392.
Each opening 394 might expose a portion of a dielectric cap 378 overlying a corresponding data line 204 to which contact is to be made with a future top contact 380 in the area of that opening 394, and might further expose a portion (e.g., at least a portion) of each adjacent (e.g., immediately adjacent) dielectric cap 378. For example, the opening 3943 might expose a portion of the dielectric cap 3783 overlying the data line 2043 to which contact is to be made with a future top contact 380 (see, e.g.,
In
In
In
Formation of the dielectric 382 might involve depositing a dielectric material of low conformability. For example, the dielectric 382 might comprise, consist of, or consist essentially of tetraethylorthosilicate (TEOS) or silane oxide. However, other dielectric materials having low conformability might alternatively be used. A dielectric material will be deemed to be of low conformability if it is expected to form voids between adjacent data lines 204 during formation of the dielectric 382 overlying the data lines 204, and is not expected to conform sufficiently to fill spaces between those adjacent data lines 204. That is, the conformability of the dielectric material being deposited to form the dielectric 382 is to be low enough that, during deposition, the dielectric material would pinch-off the spacing between the top surfaces of the dielectric caps 378 before the spacing between the data lines 204 is expected to be filled with that dielectric material, thus leaving voids 384. Note that as the width of the spacing between the dielectric caps 378 is reduced, the level of conformability can increase while still resulting in pinch-off during deposition, and thus still being deemed to be of low conformability for purposes on this disclosure. Although the dielectric 382 is depicted to be in contact with sidewalls of the data lines 204 and portions of the dielectric 376, the dielectric 382 might alternatively not contact sidewalls of the data lines 204, such that the voids 384 would extend the full width between adjacent data lines 204. Such voids 384 might further extend the full width between adjacent fins 390 of the dielectric 376. For example, during deposition, the dielectric material of the dielectric 382 might pinch off the spacing between the dielectric caps 378 before any of that dielectric material reaches the data lines 204 or the dielectric 376.
In
In
As can be seen in a comparison of
As noted with respect to
While the top contact 3803 is depicted to have a circular outline in
As is depicted in
In
In
In
Although the embodiment of
In
At 1203, a solid dielectric material might be formed between a first portion of a first data line of the plurality of data lines and a first portion of a second data line of the plurality of data lines. For example, instances of the dielectric 396 might be formed between adjacent data lines 204 as described with reference to
At 1205, a dielectric material containing a void might be formed between a second portion of the first data line and a second portion of the second data line. For example, the dielectric 382 might be formed containing voids 384 between adjacent data lines 204 as described with reference to
At 1207, a top contact might be formed overlying and in contact with the first portion of the first data line. For example, the a top contact 380 might be formed as described with reference to
Embodiments described herein facilitate a top contact 380 of sufficient size to be utilized with wafer-on-wafer (WOW) technology. In WOW technology, portions of an integrated circuit device might be formed on different substrates, e.g., support or carrier wafers. These substrates might include semiconductor substrates or dielectric substrates, for example. As one example, relevant to the present disclosure, a memory array and supporting structures might be formed on one substrate, and access circuitry for connection to the supporting structures might be formed on a different substrate. These structures might then be joined, e.g., bonded, to connect these different portions of an integrated circuit device, with a contact from one portion making a connection to a contact from the other portion. Continuing with the example, a top contact 380 of one portion of a memory formed overlying a first substrate might be bonded to a contact from a different portion of the memory, e.g., a contact to access circuitry of the memory in this example, formed overlying a second substrate distinct from the first substrate. WOW technology might further permit subsequent removal of one of the substrates, providing access for further fabrication on the resulting exposed portion of the integrated circuit device. Although outside the scope of this disclosure, such processing is described in U.S. Patent Application Publication No. US 2021/0398996 A1 to Kunal R. Parekh, published Dec. 23, 2021.
The contacts 14231-14235 might be arranged such that when the structure of
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose might be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.
Claims
1. A memory array structure, comprising:
- a first data line selectively connected to a first plurality of memory cells;
- a second data line selectively connected to a second plurality of memory cells;
- a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line;
- a second dielectric containing a void extending between a second portion of the first data line and a second portion of the second data line; and
- a top contact overlying and in contact with the first portion of the first data line.
2. The memory array structure of claim 1, wherein the first dielectric contains a different dielectric material than the second dielectric.
3. The memory array structure of claim 1, wherein the void is a first void, wherein the solid first dielectric is a first instance of the solid first dielectric, and wherein the memory array structure further comprises:
- a third data line selectively connected to a third plurality of memory cells; and
- a second instance of the solid first dielectric extending between the first portion of the first data line and a first portion of the third data line;
- wherein the second dielectric further contains a second void extending between the second portion of the first data line and a second portion of the third data line.
4. The memory array structure of claim 3, wherein the second dielectric further contains a third void extending between a third portion of the first data line and a third portion of the second data line, and a fourth void extending between the third portion of the first data line and a third portion of the third data line.
5. The memory array structure of claim 1, wherein the top contact overlies less than all of the first portion of the first data line.
6. The memory array structure of claim 5, wherein no portion of the top contact overlies the second data line.
7. The memory array structure of claim 1, wherein the solid first dielectric extends a full width of a spacing between the first portion of the first data line and the first portion of the second data line.
8. The memory array structure of claim 1, wherein the solid first dielectric extends above top surfaces of the first portion of the first data line and the first portion of the second data line, and extends below bottom surfaces of the first portion of the first data line and the first portion of the second data line.
9. The memory array structure of claim 1, wherein the void is a first void, wherein the second dielectric further contains a second void extending between a third portion of the first data line and a third portion of the second data line, wherein the first portion of the first data line is between the second portion of the first data line and the third portion of the first data line, and wherein the first portion of the second data line is between the second portion of the second data line and the third portion of the second data line.
10. A memory array structure, comprising:
- a first data line overlying and connected to a plurality of first contacts, wherein each first contact of the plurality of first contacts is selectively connected to a respective string of series-connected memory cells of an array of memory cells;
- a second data line overlying and connected to a plurality of second contacts, wherein each second contact of the plurality of second contacts is selectively connected to a respective string of series-connected memory cells of the array of memory cells;
- a third data line overlying and connected to a plurality of third contacts, wherein each third contact of the plurality of third contacts is selectively connected to a respective string of series-connected memory cells of the array of memory cells;
- a first instance of a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line;
- a second instance of the solid first dielectric extending between a second portion of the first data line and a second portion of the second data line;
- a third instance of the solid first dielectric extending between the second portion of the second data line and a first portion of the third data line;
- a second dielectric containing a first void extending between a third portion of the first data line and a third portion of the second data line, and containing a second void extending between a fourth portion of the second data line and a second portion of the third data line;
- a fourth contact overlying and in contact with the first portion of the first data line; and
- a fifth contact overlying and in contact with the second portion of the second data line.
11. The memory array structure of claim 10, further comprising:
- a fourth data line overlying and connected to a plurality of sixth contacts, wherein each sixth contact of the plurality of sixth contacts is selectively connected to a respective string of series-connected memory cells of the array of memory cells;
- a fourth instance of the solid first dielectric extending between the first portion of the first data line and a first portion of the fourth data line;
- wherein the second dielectric further contains a third void extending between the third portion of the first data line and a second portion of the fourth data line.
12. The memory array structure of claim 10, further comprising:
- a fourth instance of the solid first dielectric extending between a fifth portion of the second data line and a third portion of the third data line.
13. The memory array structure of claim 12, wherein the second void is between the third instance of the solid first dielectric and the fourth instance of the solid first dielectric.
14. The memory array structure of claim 12, wherein the third instance of the solid first dielectric and the fourth instance of the solid first dielectric are a same instance of the solid first dielectric.
15. A method of forming a portion of a memory including a memory array structure, the method comprising:
- forming a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective plurality of memory cells;
- forming a solid first dielectric material between a first portion of a first data line of the plurality of data lines and a first portion of a second data line of the plurality of data lines;
- forming a second dielectric material containing a void between a second portion of the first data line and a second portion of the second data line; and
- forming a top contact overlying and in contact with the first portion of the first data line.
16. The method of claim 15, wherein forming the solid first dielectric material between the first portion of the first data line and the first portion of the second data line comprises forming a first instance of the solid first dielectric material between the first portion of the first data line and the first portion of the second data line, and wherein the method further comprises:
- forming a second instance of the solid first dielectric material between the first portion of the first data line and a first portion of a third data line of the plurality of data lines.
17. The method of claim 16, wherein forming the top contact overlying and in contact with the first portion of the first data line comprises forming the top contact such that no portion of the top contact is overlying the second dielectric material.
18. The method of claim 15, wherein forming the solid first dielectric material between the first portion of the first data line and the first portion of the second data line comprises forming the solid first dielectric material to extend above a top surface of the first portion of the first data line and a top surface of the first portion of the second data line.
19. The method of claim 15, wherein forming the solid first dielectric material between the first portion of the first data line and the first portion of the second data line further comprises forming the solid first dielectric material to extend below a bottom surface of the first portion of the first data line and a bottom surface of the first portion of the second data line.
20. The method of claim 15, wherein the first data line has a first dielectric cap overlying the first data line, wherein the second data line has a second dielectric cap overlying the second data line, and wherein forming the solid first dielectric material between the first portion of the first data line and the first portion of the second data line further comprises forming the solid first dielectric material between a first portion of the first dielectric cap overlying the first portion of the first data line and a first portion of the second dielectric cap overlying the first portion of the second data line.
21. The method of claim 20, wherein forming the second dielectric material containing the void between the second portion of the first data line and the second portion of the second data line further comprises forming the second dielectric material containing the void between a second portion of the first dielectric cap overlying the second portion of the first data line and a second portion of the second dielectric cap overlying the second portion of the second data line.
22. The method of claim 21, further comprising removing the first portion of the first dielectric cap prior to forming the top contact overlying and in contact with the first portion of the first data line.
23. The method of claim 15, wherein forming the plurality of data lines comprises:
- forming a third dielectric material overlying a plurality of first contacts, wherein each first contact of the plurality of first contacts is selectively connected to a respective string of series-connected memory cells;
- forming a plurality of second contacts in the third dielectric material such that each second contact of the plurality of second contacts is in contact with a respective first contact of the plurality of first contacts;
- forming a conductive material overlying the third dielectric material, and overlying and in contact with the plurality of second contacts;
- forming a fourth dielectric material overlying the conductive material; and
- patterning the fourth dielectric material, the conductive material, and the third dielectric material to define a plurality of fins of the third dielectric material, the plurality of data lines from the conductive material with each data line of the plurality of data lines overlying a respective fin of the plurality of fins, and a plurality of dielectric caps from the fourth dielectric material with each dielectric cap of the plurality of dielectric caps overlying a respective data line of the plurality of data lines;
- wherein each fin of the plurality of fins contains one or more second contacts of the plurality of second contacts.
24. The method of claim 15, wherein forming the second dielectric material comprises forming a dielectric material of low conformability for a spacing between the first data line and the second data line.
25. The method of claim 15, further comprising bonding the top contact to a contact of an integrated circuit structure using wafer-on-wafer technology.
26. The method of claim 25, wherein bonding the top contact to the contact of the integrated circuit structure comprises bonding the top contact to a contact of the integrated circuit structure configured to provide connection of the top contact to access circuitry of the memory.
27. The method of claim 15, wherein the plurality of memory cells are formed overlying a first substrate, and wherein the method further comprises:
- bonding the top contact to a contact of an integrated circuit structure;
- wherein the integrated circuit structure is formed overlying a second substrate distinct from the first substrate.
28. A memory, comprising:
- an array of memory cells;
- a first data line selectively connected to a first plurality of memory cells of the array of memory cells;
- a second data line selectively connected to a second plurality of memory cells of the array of memory cells;
- a third data line selectively connected to a third plurality of memory cells of the array of memory cells;
- a first instance of a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line;
- a second instance of the solid first dielectric extending between the first portion of the first data line and a first portion of the third data line;
- a second dielectric containing a first void extending between a second portion of the first data line and a second portion of the second data line, a second void extending between the second portion of the first data line and a second portion of the third data line, a third void extending between a third portion of the first data line and a third portion of the second data line, and a fourth void extending between the third portion of the first data line and a third portion of the third data line;
- a top contact overlying and in contact with the first portion of the first data line; and
- a controller for access of the array of memory cells.
29. The memory of claim 28, wherein the top contact is a first top contact, and wherein the memory further comprises:
- a fourth data line selectively connected to a fourth plurality of memory cells of the array of memory cells;
- a third instance of the solid first dielectric extending between a fourth portion of the first data line and a fourth portion of the third data line;
- a fourth instance of the solid first dielectric extending between the fourth portion of the third data line and a first portion of the fourth data line; and
- a second top contact overlying and in contact with the fourth portion of the third data line;
- wherein the second dielectric further contains a fifth void extending between a fifth portion of the first data line and a fifth portion of the third data line, a sixth void extending between the fifth portion of the third data line and a second portion of the fourth data line, and a seventh void extending between a sixth portion of the third data line and a third portion of the fourth data line.
30. The memory of claim 28, wherein the top contact is a first top contact, and wherein the memory further comprises:
- a fourth data line selectively connected to a fourth plurality of memory cells of the array of memory cells;
- a third instance of the solid first dielectric extending between a fourth portion of the third data line and a first portion of the fourth data line; and
- a second top contact overlying and in contact with the fourth portion of the third data line;
- wherein the second dielectric further contains a fifth void extending between a fifth portion of the third data line and a second portion of the fourth data line, and a sixth void extending between a sixth portion of the third data line and a third portion of the fourth data line.
31. The memory of claim 28, further comprising an additional contact bonded to the top contact in a wafer-on-wafer configuration.
32. The memory of claim 31, wherein the additional contact is configured to provide connection of the top contact to access circuitry of the memory.
33. The memory of claim 32, wherein the access circuitry comprises a buffer portion of the memory.
Type: Application
Filed: Oct 6, 2022
Publication Date: Feb 29, 2024
Applicant: MICRON TECHNOLOGY, INC. (Boise, ID)
Inventor: Shyam Surthi (Boise, ID)
Application Number: 17/961,025