Hierarchical cache memory system and method for controlling data coherency between a primary and a secondary cache

- Fujitsu Limited

A hierarchical memory system having a cache memory for storing a portion of data stored in a main memory. The cache memory is divided into hierarchically ordered primary and secondary cache memories. The primary cache memory being connected to a processor. The larger secondary cache memory being connected to the primary cache memory and to a bus connected to the main memory. When a cache miss-hit is made in the secondary cache memory, at the time of access by the processing unit, the secondary cache memory notifies the primary cache memory of an address of a replacement entry prior to seeking a data transfer. The primary cache memory, when it has an entry corresponding to the replacement entry, makes the corresponding entry the replacement entry. When the primary cache memory does not have an entry corresponding to the replacement entry, the primary cache memory makes an entry based on a predetermined replacement priority and then enters data transferred from the secondary cache memory into the replacement entry.

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Claims

1. A hierarchical cache memory system in which a processing unit performs processing independent of a system bus to which a main memory is connected, the hierarchical cache memory system comprising:

a primary cache memory connected to the processing unit to which the processing unit makes direct access;
a second cache memory connected between said primary cache memory, said main memory and the system bus such that the processing unit cannot accesses the system bus except through said secondary cache memory; and
a first entry rewrite control means, provided in said primary cache memory, for receiving an address corresponding to a replacement entry, which is an entry to be invalidated, from said secondary cache memory when a cache miss-hit is made in said secondary cache memory and when said primary cache memory has a corresponding entry to the replacement entry, making the corresponding entry the replacement entry otherwise setting the replacement entry based on a predefined replace priority; and
a second entry rewrite control means, provided in said secondary cache memory, for transferring the address of the replacement entry to said primary cache memory prior to a transfer of data to said primary cache memory when said cache miss-hit is made in said secondary cache memory;
wherein when said secondary cache memory has a first entry corresponding to an address in the main memory which is to be rewritten, said second entry rewrite control means makes the first entry invalid and directs said primary cache memory to make a corresponding entry invalid and outputs the address of the first entry to said primary cache memory, and said first entry rewrite control means invalidates the corresponding entry in said primary cache memory.

2. A hierarchical cache memory system in which a processing unit performs processing independent of a system bus to which a main memory connected, the hierarchical cache memory system comprising;

a primary cache memory to which the processing unit makes direct access;
a secondary cache memory connected between said primary cache memory and the main memory such that the processing unit cannot accesses the system bus except through said second cache memory; and
a first entry rewrite control means provided in said secondary cache memory for transferring the address of a replacement entry to said primary cache memory prior to a transfer of data to said primary cache memory when a cache miss-hit is made in said secondary cache memory; and
a second entry rewrite control means, provided in said primary cache memory, for receiving an address corresponding to a replacement entry, which is an entry to be invalidated, from said secondary cache memory when said cache miss-hit is made in said secondary cache memory and when said primary cache memory has a corresponding entry to the replacement entry, making the corresponding entry the replacement entry otherwise setting the replacement entry based on a predefined replace priority;
wherein when said secondary cache memory has a first entry corresponding to an address in the main memory which is to be rewritten, said second entry rewrite control means makes the first entry invalid and directs said primary cache memory to make a corresponding entry invalid and outputs the address of the first entry to said primary cache memory, and said first entry rewrite control means invalidates the corresponding entry in said primary cache memory.

3. A hierarchical cache memory system in which a processing unit performs processing independent of a system bus to which a main memory is connected, the hierarchical cache memory system comprising:

a primary cache memory to which the processing unit makes direct access;
a secondary cache memory connected between said primary cache memory, said main memory and said system bus such that the processing unit cannot accesses the system bus except through said secondary cache memory;
said primary cache memory including a first entry rewrite control means to receive the address of a replacement entry from said secondary cache memory when a cache miss-hit is made in said secondary cache memory and when said primary cache memory has a corresponding entry to the replacement entry, making the corresponding entry the replacement entry otherwise setting the replacement entry based on a predetermined replace priority; and
said secondary cache memory including a second entry rewrite control means which, when a cache miss-hit is made in said secondary cache memory, transfers the address of the replacement entry to said primary cache memory prior to a transfer of data to said primary cache memory;
wherein when said secondary cache memory has a first entry corresponding to an address in the main memory which is to be rewritten, said second entry rewrite control means makes the first entry invalid and directs said primary cache memory to make a corresponding entry invalid and outputs the address of the first entry to said primary cache memory, and said first entry rewrite control means invalidates the corresponding entry in said primary cache memory.

4. The system according to claim 3, wherein at least one entry of said primary cache memory has a data capacity equal to that of said secondary cache memory.

5. A method of controlling a hierarchical memory system having a cache memory divided into a hierarchically-ordered primary cache memory and a larger secondary cache memory comprising steps of:

accessing a main memory and a system bus solely through the primary cache memory;
notifying the primary cache memory of an address of a replacement entry prior to transferring data from the secondary cache memory when a cache miss-hit is made in the secondary cache memory at the time of access by a processing unit;
if a corresponding entry exists in the primary cache memory, making the corresponding entry a replacement entry in the primary cache memory;
if a corresponding entry does not exist in the primary cache memory, making an entry based on a predetermined replace priority, the replacement entry in the primary cache memory; and
entering data transferred from said secondary cache memory into the replacement entry in said primary cache memory;
if an address in said main memory is to be rewritten and the secondary cache memory bag a first entry corresponding to the address making the first entry invalid, directing the primary cache memory to make the first entry invalid, and outputting the address of the first entry to said primary cache memory; and
if the primary cache memory has a second entry corresponding to the first entry, making the second entry invalid.

6. The method according to claim 5, wherein said processing unit access the secondary cache memory using read or write access.

7. A hierarchical cache memory system comprising:

a processor unit having an operating unit;
a first cache memory for storing entries of data stored in a main storage said operating unit accessing an external system bus through said first cache memory, wherein
said first cache memory comprises:
an access control unit for replacing an entry in the cache memory where an entry corresponding to an address corresponding to a replacement entry has been informed externally when a cache miss-hit occurs, making the corresponding entry a replacement entry, if no corresponding entries exist in the cache memory, determining a replacement entry based on a predetermined order of priority, and then entering externally transmitted data in the replacement entry;
a first memory for storing the entries;
a first address tag unit for storing an address of data stored in said first memory;
a first comparing unit for comparing an address outputted by said processor unit with an address stored in said first address tag unit and determining if a cache hit is made; and
a second memory for storing the entries;
a second address tag unit for storing an address of data stored in said second memory;
a second comparing unit for comparing an access address to said main storage when a cache miss-hit takes place in said first cache memory, with an address stored in said second address tag unit, and for determining if a cache hit has been made; and
access control means for outputting to said first cache memory an address of a replacement entry when said second comparing unit determines that no cache hit is detected, and then transmitting the data.

8. The hierarchical cache memory system according to claim 7, wherein said cache memory comprises:

a least recently used data memory for storing least recently used data at said address stored in said first address tag unit; and
a least recently used data write generating circuit for assigning a highest priority to an entry involved in a cache hit, and nullifying an entry involved in one of a cache miss-hit and an invalid cache hit.
Referenced Cited
U.S. Patent Documents
4996641 February 26, 1991 Talgam et al.
5136700 August 4, 1992 Thacker
5276848 January 4, 1994 Gallagher et al.
5285323 February 8, 1994 Hetherington et al.
5307477 April 26, 1994 Taylor et al.
5325503 June 28, 1994 Stevens et al.
5359723 October 25, 1994 Mathews et al.
5367659 November 22, 1994 Iyengar et al.
5369753 November 29, 1994 Tipley
5386547 January 31, 1995 Jouppi
5434992 July 18, 1995 Mattson
Patent History
Patent number: 5829024
Type: Grant
Filed: Jul 8, 1996
Date of Patent: Oct 27, 1998
Assignee: Fujitsu Limited (Kawasaki)
Inventor: Taizo Sato (Kawasaki)
Primary Examiner: Tod R. Swann
Assistant Examiner: Tuan V. Thai
Law Firm: Staas & Halsey
Application Number: 8/676,506
Classifications
Current U.S. Class: Hierarchical Caches (711/122); Hierarchical Memories (711/117); Caching (711/118); Control Technique (711/154); Least Recently Used (lru) (711/160)
International Classification: G06F 1208; G06F 1300;