Content addressable memory with hashing function
A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.
Latest NetLogic Microsystems, Inc. Patents:
- Weighted instruction count scheduling
- Packet format for error reporting in a content addressable memory
- TCP segmentation offload (TSO) using a hybrid approach of manipulating memory pointers and actual packet data
- Content addressable memory having column segment redundancy
- REDUCING LATENCY ASSOCIATED WITH TIMESTAMPS
The present invention relates generally to information retrieval systems and more particularly to content addressable memory devices.
BACKGROUNDContent addressable memory (CAM) devices are often used to support packet forwarding and classification operations in network switches and routes. A CAM device can be instructed to compare a search value, typically formed from one or more fields within the header of an incoming packet, with entries within an associative storage array of the CAM device. If the search value matches an entry, the CAM device generates an index that corresponds to the location of the matching entry within the storage array, and asserts a match flag to signal the match. The index may then be used to address another storage array, either within or separate from the CAM device, to retrieve routing or classification information for the packet.
Referring to
Although the integration of compare and storage circuits within each CAM cell 107 enables simultaneous, multi-row searching within the CAM array, the additional transistors required to implement the compare circuit significantly increases the size of the cell 107, reducing the memory density that can be achieved within the CAM device. Also, because each compare circuit in each row of CAM cells is simultaneously activated during a search operation, a relatively large amount of power is required to perform a search. This power consumption results in heat generation that further limits the storage density that can be achieved within the CAM device (i.e., due to thermal constraints).
The features and advantages of the present invention are illustrated by way of example and are by no means intended to limit the scope of the present invention to the particular embodiments shown, and in which:
In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the present invention. In some instances, the interconnection between circuit elements or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be single signal lines, and each of the single signal lines may alternatively be buses. A signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘{overscore (<signal name>)}’) is also used to indicate an active low signal. Active low signals may be changed to active high signals and vice-versa as is generally known in the art.
A hash CAM device that includes a memory and hash circuitry to associated a search value with a unique location within the memory is disclosed in numerous embodiments. In contrast to the prior art CAM device described above, a search value is not compared with each entry within an array of CAM cells to locate a matching entry, but rather the search value is input to a hash index generator which generates a search index (i.e., address) to the memory based on the search value itself. Each value stored within the memory was similarly input to the hash index generator to generate a storage index (i.e., memory address at which the value is stored) so that, if the search value matches a previously stored value, the search index and storage index will match. Accordingly, a match may be detected by comparing the search value with the entry stored at the search index. If the entry and search value match, a match flag is asserted to indicate the match detection and the search index is output as the match address. Because compare circuits need not be included within each storage cell of the device memory, a significantly higher memory density may be achieved in the hash CAM device than in the prior art CAM device described above. Also, because a search value is compared with only one memory entry per search (as opposed to comparing a search value with all entries within a CAM array), significantly less power is required to search the hash CAM device than the prior art CAM devices described above.
Overview of a Hash CAM device
Each data value stored in the memory 133 is referred to herein as an entry (shown generally at 132) and includes at least a key, KEY, and validity value, V. The key is formed from selected bits within the input data value and is input, at least in part, to the hash index generator 131 to generate the hash index at which the entry is stored (i.e., the storage index). The validity value may include one or more bits and is used to indicate the presence of a valid entry. An entry 132 may optionally include mask information, MSK (e.g., a mask value to be applied during a comparison operation, or an encoded value that can be decoded to generate a mask value), a prior value, PRI, which is a numeric value that indicates a priority of the entry relative to other entries, and control/configuration information, CNTRL/CFG, that may be used to control certain operations within the hash CAM device 130. The priority values included within the various entries within the memory 133 may be assigned in ascending priority order (i.e., lower numeric values indicate a higher priority than higher numeric values) or descending priority order (i.e., higher numeric values indicate a higher priority than lower numeric values). In the description that follows ascending priority order to generally assembled, though descending priority order may be alternatively by used. Also, in alternative embodiments, non-numeric values may be used to indicate priority (e.g., codewords or other indications of priority may be used).
Loading and Searching the Hash CAM
The hash index generator 131 ideally generates a unique storage index for each value to be loaded into the memory 133. For most applications, however, it is desirable for the hash index to be smaller (i.e., contain fewer constituent bits) than the corresponding input value, meaning that two or more different input values may yield the same storage index; an event referred to herein as a collision. Accordingly, before loading an input value into the memory 133, it is desirable to determine whether the input value will yield an index to an occupied or unoccupied storage location within memory 133 (i.e., determine whether a collision will occur). Otherwise, a previously loaded entry may be unknowingly overwritten. In one embodiment, a collision determination is achieved through a special type of search operation referred to herein as a next free address (NFA) operation. In a NFA operation, the value to be stored, referred to herein as an entry candidate, is provided in whole or part to the hash index generator 131 to produce a hash index 136. The entry, if any, at the indexed location (i.e., the storage location within memory 133 indicated by the hash index) is output to the compare logic 135 which, in turn, asserts or deasserts the match flag 134 according to the state of the validity value of the entry. If the validity value indicates the presence of a valid entry, a collision between the entry candidate and an existing entry (i.e., a previously loaded entry) has occurred, and the compare logic 135 deasserts the match flag 134 to indicate the conflicting occupation of the indexed memory location and that the candidate input value cannot be stored. If the validity value does not indicate the presence of a valid entry, the compare logic 135 asserts the match flag 134 to indicate that the indexed memory location is unoccupied. The candidate input value is subsequently stored in the memory 133 at the indexed location in an operation referred to herein as an insert operation.
During a search operation, a search value received via the data bus is input to the hash index generator to generate a hash index 136 referred to herein as a search index. The indexed entry 138 (i.e., entry at the location indicated by the search index) is output to the compare logic 135 which compares the entry with the search value. If the entry matches the search value, the match flag 134 is asserted to indicate the match condition. The search index (i.e., hash index 136) is output as the match address and may be used to access an associated storage 111, for example, to retrieve forwarding, classification, policing or other information associated with the entry. If the entry does not match the search value, the match flag 134 is deasserted to indicate that no match was detected within the hash CAM device 130 and, for example, may be used to quality the reach from the associated storage 111.
In one embodiment, the assembler circuit 191 assembles the key, mask information, priority and/or control/configuration values (referred to herein as entry components) from potentially dispersed fields of bits within an incoming data value. An entry type value programmed within the configuration register 137 indicates the location of the bit fields within the incoming data value and is provided to the assembler circuit 191 to enable the assembler circuit to properly assemble the entry components of differently formatted data types (e.g., IPv4 (Internet Protocol version 4), IPv6 (Internet Protocol version 6), MPLS (Multiprotocol Label Switching), etc.). The complete set of assembled entry components constitutes an entry 208 and is output from the assembler circuit to a read/write circuit 197 within the memory 133 for storage in an insert operation. The assembler circuit 191 also outputs the assembled key 192 to the key mask logic 193, and to the compare logic 135. The key provided to the compare logic 135 is referred to herein as a search key 210. Note that, in one embodiment, the key 192 and search key 210 are the same assembled portion of an incoming value, but are nonetheless referred to herein by different names and reference numerals.
The key mask logic 193 receives the key 192 from the assembler circuit 191 and masks selected portions of the key according to a key mask value programmed within the configuration register 137. The resulting masked key 194 is provided to the hash index generator 131. The hash index generator 131 generates a hash index 136 based on the masked key 134. As discussed above, the hash index is used during NFA and search operations to access to location within the memory 133.
In one embodiment, Q equally sized bit fields, KF1-KFQ, within the key 192 are selectively masked by the key mask logic 193 according to a key mask value stored in the configuration register. In one embodiment, for example, each of the Q fields is a 4-bit field that is selectively masked (i.e., forced to a predetermined logic state) by a corresponding bit, B1-BQ, within the key mask value. In the key mask logic 193 of
Extending the embodiment to cover ternary searches presents some challenges. In a ternary search, some of the bit fields of a search key (or other portion of the search value) may be masked and are considered as don't cares during a search operation. In the following description, the unmasked portion of a key is called the invariant portion and the masked portion (don't care portion) is called the variant portion. If the hash index were to be calculated on the entire search key, (including the variant and invariant portions of the entry) then the hash index when inserting an entry can potentially be different than the hash index calculated during a search, even through the search value may match the entry (i.e., when selected bits are masked during the compare operation). From a search perspective, introducing the key mask logic 193 effectively isolates the invariant portions of the key 192 both in the insertion as well as the search operations, forming the basis for generation of a unique hash index for each input value. It is not necessary to use the entire invariant portion of the key for hash index generation; it can be a sub-set of the invariant portion. As an example, consider Table 1 below which illustrates how the key mask is chosen and illustrates the operation of a key mask logic circuit. The entries are ternary entries and the variant portions are shown with an ‘X’. Each bit of an 8-bit key mask value corresponds to a respective 4-bit field within a 32-bit input key (the symbol ‘h’ indicates hexadecimal notation and the symbol ‘b’ indicates binary notation):
In the above example, the key mask value masks the first and last bytes (i.e., 8 bits) of the input key, thereby establishing the first and last bytes as the variant (don't care) components of the entries and the middle two bytes of the entries as the invariant components of the input key. Note that if two entries are identical after going through the key mask circuit, they will, as in the example above, yield identical hash indices. Conversely, if two inputs keys have different invariant portions, the masked keys will be different and, in general, will yield different hash indices.
As can be seen, the key mask value may be chosen so that the variant portion of all the entries in the search table are in effect set to a known, pre-defined value (in this case binary 0). The search process can be illustrated with an example. If the search key of FF5A5A3Ch is presented, this key goes through the same key mask circuit and will generate the same index as entry #2 in the table, and will also result in a match.
Thus, by programming the key mask value to define a desired invariant component (or components) within an input key, a degree of key masking (i.e., in the variant components) may be achieved within the hash CAM device. This key masking feature may be used to achieve ternary CAM operation within a system that contains multiple hash CAM devices by programming a different key mask value into the configuration register of each hash CAM device, and storing each input value in a CAM device selected according to the invariant/variant key components of the input value. For example, a first hash CAM device may be assigned a key mask value that defines bits 24-31 of an IPv4 destination address as a don't care field (i.e., variant key component) and bits 0-23 of the destination address as a invariant key component, while a second hash CAM device may be assigned a key mask value that defines bits 16-23 of the IPv4 destination address as variant key component, and bits 0-15 and 24-31 as a invariant key component. Thereafter data values may be loaded into either the first hash CAM device or the second hash CAM device according to whether bits 24-31 or 16-23 may be masked during a search operation. This technique for achieving ternary CAM operation is discussed in further detail below.
Still referring to
Still referring to
Referring again to
The address decoder 195 receives the hash index 136 from the hash index generator 131 and decodes the hash index to activate one of the word lines 204. The activated word line switchably couples a corresponding row of storage elements within the memory array 201 to the bit lines 206, thereby enabling read and write access to the storage elements (i.e., the selected row). In a memory read, for example, during a NFA or search operation, the contents of the selected row is output via the bit lines 206 to a bank of sense amplifiers within the read/write circuit 197. The sense amplifiers sense the contents of the selected row and output the sensed data to the compare logic as entry 138. In a memory write (e.g., during an insert operation), a bank of write drivers within the read/write circuit 197 drives an entry 208 onto the bit lines for storage within the selected row.
Returning again to
The multi-mode comparator receives the entry key 246 and search key 210 and compares the two keys in accordance with the mask value selected by multiplexer 245 and the compare mode indicated by the compare mode value. If entry key and search key are determined to match one another (i.e., after any masking specified by the compare mode and mask value), the multi-mode comparator asserts a match signal 250 to indicate the match detection. If the entry key and search key are determined not to match, the match signal is deasserted. The match signal 250 is logically ANDed with an active low validity value 242 in AND gate 247 to generate a qualified match signal 252. Thus, only a match between the search key and the key of a valid entry will result in assertion of the qualified match signal 252. Multiplexer 249 selects either the qualified match signal 252 or the validity value 242 to be output as a match/empty value 134 according to the state of the NFA signal 212. Thus, when the NFA signal is high (i.e., during a NFA operation), the state of the validity value is output by multiplexer 249 to indicate whether or not the memory location selected by the hash index is occupied. During a search operation, when the NFA signal is low, the qualified match signal 252 is output to indicate whether a match was detected.
Still referring to
In one embodiment, the multimode comparator 243 is capable of performing different types of comparisons according to the programmed compared mode value. Fore example, the compare mode value may indicate a binary comparison, ternary comparison (i.e., comparison in which mismatch conditions are ignored for selected bit positions), range comparisons (i.e., comparison to determine whether search key is greater than or less than a given value) or any combination of binary, ternary and/or range comparisons. In an application where less than all types of comparisons are needed, the multi-mode comparator 243 may be replaced by a comparator that performs only the needed types of comparisons.
When the match compare cell 285 is enabled, transistors 276, 278, 277, 279, and 281 cooperate to perform a maskable comparison of the search key bit and entry key bit. Transistor 281 is coupled to receive the complement mask bit, /M, so that when the complement mask bit is low (i.e., mask bit high to mask the compare operation), transistor 281 is switched off, and transistors 276, 278, 277 and 279 are prevented from pulling the match line low, thereby masking any mismatch indication. By contrast, when the active low mask bit is high (i.e., mask bit low to unmask the compare operation), transistor 281 is turned on to enable transistors 276, 278, 277 and 279 to pull the match line 256 low in the event of a mismatch between the search key bit and entry key bit. For example, if the entry key bit is high and the search key bit is low, transistors 279 and 277 will be switched on, pulling the match line low through transistors 281 and 282. Alternatively, if the search key bit is high and the entry key bit is low, transistors 276 and 278 will be switched on, pulling the match line through transistors 281 and 282.
The range compare cell 275, when enabled, signals an out-of-range condition by asserting a logic low signal (GTi) on GT line 260i if either (1) the search key bit is greater than the entry key bit, or (2) the search key bit and entry key bit are equal and a greater-than signal (GTi-1) from a less significant compare cell is low. More specifically, if the search key bit is high and the entry key bit is low (i.e., if the search key bit is greater than the entry key bit), then transistors 262 and 264 are switched on to form, along with enabling transistor 267, a path between the GT line 260i and ground, thereby pulling the GT line 260i low. Transistors 266 and 268 are used to couple the GTi-1 signal on input GT line 260i-1 to the GT line 260i if the search key bit and entry key bit are equal. That is, if the search key bit is high (meaning that the search key bit must either be equal to or greater than the search key bit), transistor 266 is switched on to enable the GTi-1 signal onto the GT line 260i, and if the entry key bit is low (again meaning that the search key bit is equal to or greater than the entry key bit), then transistor 268 is switched on to enable the GTi-1 signal onto the GT line 260i. Thus, if either transistor 266 or 268 is switched on, a low GTi-1 signal (indicating that a less significant portion of the search key component is greater than a corresponding less significant portion of the entry key component), will be propagated to the GT line 260i of range compare cell 275. Referring to
Note that the compare cells 2571-257S may alternatively pull the match line low in response to detecting that the search key component is less than the entry key component (i.e., signal a less-than (LT) condition). Referring again to
In another embodiment, both out-of-range conditions, GT and LT, may be signaled by a single compare cell by using the mask bit to indicate the lower (or upper) boundary of the range definition. In yet another embodiment, a selection may be made between GT and LT range comparisons by selectively multiplexing the key bits applied to transistors 262, 264, 266 and 268. Also, the mask transistor 281 may be omitted from the match compare cell 285 in an alternative embodiment in which maskable compare (i.e., ternary compare) operation is not needed.
Referring again to
Reflecting on the operation of the hash CAM devices of
Overflow CAM
Reflecting on the operation of the hash CAM devices described in reference to
The CAM device 300 also includes a device flag circuit 305 and device priority logic 307. The device flag circuit 305 receives the block flags from the hash CAM and overflow CAM blocks and logically combines the block flags to generate a device flag 304 (DF). In one embodiment, the block flags are combined in an OR operation so that, if either CAM block indicates a match condition, the device flag circuit 305 will assert the device flag 304. The device flag 304 may also be asserted to indicate a full/empty status for the CAM device 300 (e.g., during a non-search operation), or a separate signal or signals may be output for such purposes. Further, additional flags may be output by the flag logic such as a multiple match flag (to be asserted, for example, when more than CAM block indicates a match condition), an almost full flag (to be asserted, for example, when a CAM block reaches a predetermined fill-level), and so forth. The device priority logic 307 receives the block flags, block priority values and block indices from the hash CAM and overflow CAM blocks, and outputs, as a device priority value 306 (DP), a highest priority one of the block priority values for which the corresponding block flag is asserted. The device priority logic 307 also outputs a device index 308 (DIN) that includes a block identifier (block ID) component and a block index component. The block identifier component is a block address that corresponds to the CAM block (301 or 303) that sourced the device priority value, and the block index component is the block index (BINHC or BINOFC) output by the CAM block indicated by the block ID.
In response to a load instruction (or NFA instruction in the case of a two-phase load embodiment), the instruction decoder 309 initiates a NFA operation within the hash CAM block 301 to determine whether the hash CAM block 301 is conflicted. In response, the hash CAM block outputs 301 a block index (BINHC) and a block flag (BFHC) that indicates whether the indicated memory location is empty or occupied. In one embodiment, the instruction decoder 309 does not enable the overflow CAM block 303 to participate in the NFA operation so that the overflow CAM block 303 does not assert a block flag. Consequently, during the NFA operation, the device flag circuit 305 outputs a device flag 304 that corresponds to the state of the hash CAM block flag (BFHC) and the device priority logic 307 outputs a device index 308 that includes a block ID that corresponds to the hash CAM block 301 and the hash CAM block index (BINHC). Thus, after a NFA operation within the CAM device 300, the device flag 304 will indicate whether a candidate entry may be stored in the hash CAM block 301 and, if so, the device index 308 will indicate the location within the hash CAM block 301 at which the entry may be inserted (i.e., the insertion address). In a two-phase load embodiment, the host may respond to an asserted device flag signal by issuing an insert instruction to insert the candidate entry at the indicated location within the hash CAM block 301. If the device flag is not asserted, the host may issue an instruction to insert the entry candidate into the next free address within the overflow CAM block 303. In one embodiment, during an insertion into the overflow CAM block 303, the overflow CAM block 303 outputs a next free address (i.e., available location within the overflow CAM block) and a block flag (BFOFC) that indicates whether the overflow CAM is full. The overflow CAM block flag is output by device flag circuit 305 as the device flag 304 (the block flag from hash CAM block 301 being deasserted) so that a host device may determine when the overflow CAM block 303 becomes full and cease further instructions to insert collision-producing entry candidates into the overflow CAM block 303.
In an alternative embodiment of the hash CAM device 300, the overflow CAM block 303 participates in a NFA operation by asserting its block flag signal, BFOFC, if the overflow CAM block 303 is not full and by outputting the next free address within the overflow CAM as block index, BINOFC. The overflow CAM block 303 further outputs a predetermined block priority value, BPOFC, that is lower than the priority value output by an unconflicted hash CAM block 301. By this arrangement, so long as the overflow CAM block 303 is not full, the CAM device 300 will always assert the device flag signal in response to a NFA instruction, and the device priority logic will select, according to which CAM block (301 or 303) outputs the highest priority block priority value in combination with an asserted block flag, one of the block indices, BINHC or BINOFC, to form the block index component of the device index 308, and will generate a block ID that corresponds to the selected block index. Thus, if the device flag 304 is asserted in response to a NFA instruction, the host device may instruct the CAM device 300 to store the entry candidate at the block and storage location indicated by the device index 308. Note that, in a unified load embodiment, the instruction decoder 309 (or other control circuit within the CAM device 300) may respond to assertion of the device flag 304 and device index 308 by signaling the indicated CAM block (301 or 303) to store the candidate entry at the indicated block index. In either embodiment (i.e., unified or two-phase load), a collision within the hash CAM block 301 will not prevent the CAM device 300 from being able to store an incoming data value. Also, from the perspective of a host device, the unified load embodiment of CAM device 300 responds to a load request by carrying out the instructed load operation. The host device (and therefore the system designer) need not know that the CAM device 300 searches for an insertion address, and system level operation is not impacted by which of the hash CAM block 301 and the overflow CAM block 303 is ultimately selected for entry insertion.
Using Multiple Hash CAM Blocks to Achieve Ternary CAM Operation
As discussed above in reference to
As discussed above in reference to
In one embodiment, a variant key definition is assigned to a given hash CAM block by programming a corresponding key mask value into the configuration register of the CAM block. Thereafter, as part of a NFA operation, the key mask value within each CAM block is compared with a mask code that indicates a variant key definition for the entry candidate (i.e., the mask code indicates which bits within the key of the entry candidate may be masked). Using this approach, the key mask value programmed within each CAM block effectively allocates the hash CAM block to a logical group of hash CAM blocks (or at least one hash CAM block) referred to herein as a mask pool.
The entry type value programmed within the configuration register of each hash CAM block also allocates the hash CAM block to a logical group of one or more hash CAM blocks referred to herein as an entry type pool. In one embodiment, each hash CAM block is allocated to one of a finite number of entry type pools which are used to store only entries having the programmed entry type. For example, a first set of hash CAM blocks may be allocated (i.e., by appropriate assignment of entry type values within their respective configuration registers) to an IPv4 pool, a second set of hash CAM blocks may be allocated to an MPLS pool, a third set of hash CAM blocks may be allocated to a packet classification pool, a fourth set of hash CAM blocks may be allocated to an IPv6 pool, and so forth. Any hash CAM block, in any physical order, can be assigned to any entry type pool.
During a NFA operation, the programmed entry type and key mask value of each hash CAM block are compared with the entry type and key mask value of the entry candidate. Only those hash CAM blocks which fall within the mask pool and entry type pool indicated by the entry candidate are enabled to participate in the NFA operation, with all other CAM blocks being disabled from asserting their block flags (i.e., disabled from indicating an ability to store the candidate entry). Thus, all hash CAM blocks configured with the same key mask value and entry type define a logical pool, called an insertion pool, into which an entry having a matching key mask value and entry type may be asserted.
During a search operation, the entry type for an incoming search value is compared with the entry type of each hash CAM block, and only those hash CAM blocks which have been programmed with a matching entry type are enabled to participate in the search. That is, all hash CAM blocks which do not fall within the indicated entry type pool are disabled from signaling a match.
CAM Device with Multiple Hash CAM Blocks
The hash CAM block 319 further includes block select logic 331 to generate a block select signal 332 according to an incoming search ID value 330 (SID). In one embodiment, the search ID 330 is incorporated or encoded within the operation code or operand of an incoming NFA instruction or search instruction. In a NFA instruction, the search ID includes a mask code and class code that correspond to a key mask value and entry type value, respectively, and therefore specify an insertion pool. The block select logic compares the mask code and class code against the key mask and entry type values, respectively, programmed into the configuration register 137. If the specified codes match the programmed values, the block select logic 331 asserts the block select signal 332 to enable the output logic 335 to assert the block flag 338 (i.e., if no collision is detected). If the codes do not match the programmed values (i.e., the specified insertion pool does not match the programmed insertion pool), the block select logic 331 deasserts the block select signal 332 to disable the output logic 335 from asserting the block flag 338, thereby preventing the hash CAM block from being selected for entry insertion.
In a search instruction, the search ID includes a class code, but no mask code. Accordingly, the block select logic 331 compares only the programmed entry type value with the class code. If the class code and programmed entry type match (i.e., programmed entry type pool matches the search-specified entry type pool), the block select signal 332 is asserted to enable the output logic 335 to assert the block flag 338 (i.e., if a match is detected between search value and entry). If the programmed and specified entry type pools do not match, the block select signal 332 is deasserted to disable the output logic 335 from asserting the block flag 338. Note that, in alternative embodiments, the block select signal 332 may be applied to any other circuit blocks within the hash CAM block to prevent operation of those circuits (e.g., to save power) in the event of a mismatch between the search ID and programmed value(s).
During a search operation, the NFA signal is low so that the multiplexer 349 selects the output of comparator 343 to set the state of the block select signal 332. Consequently, during a search operation, the block select signal 332 will have a high or low state according to whether the entry type pool specified by the search ID matches the entry type pool indicated by the programmed entry type value.
The block priority value 336 output during a NFA operation is referred to herein as an insert priority value, and is compared with insert priority values output by other hash CAM blocks to select one of a number of available hash CAM blocks to store the input value. During a search operation, by contrast, the priority component (PRI) of the indexed entry 138 (referred to as a search priority value) is output as the block priority value 336. The output logic 335 includes a multiplexer 359 to select, either an insert priority value or the search priority value to be output as block priority value 336 according to the state of the NFA signal 212. That is, if the NFA signal is low, indicating a search operation, the priority component of entry 138 is selected to be output as the block priority value 336. If the NFA signal is high, indicating a NFA operation, an insert priority value is selected. In one embodiment, the insert priority value is a predetermined priority value (zero in this example). Alternatively, in an embodiment that implements a capacity-dependent insertion policy, the insert priority value is maintained in a R-bit fill counter 357 that is incremented in response to an insertion operation within the hash CAM block (in which case signal WR is asserted, for example, by the instruction decoder) and decremented in response to a delete operation within the hash CAM block (in which case signal DEL is asserted). Thus, the insertion priority value indicates the fill level of the hash CAM block, and, when output as block priority value 336, enables the device priority logic 325 of
The priority compare circuit also outputs a plurality of qualified match signals 3661-366N+1, each of which corresponds to a respective one of the N+1 CAM blocks (i.e., match signals 3661-366N correspond to the N hash CAM blocks 319 and match signal 366N+1 corresponds to the overflow CAM block 321). Each qualified match signal, if asserted, indicates that the corresponding CAM block sourced (i.e., output to the priority compare circuit) the device priority number. The priority encoder 363 encodes the qualified match signals into a block identifier (BID) that identifies the CAM block that sourced the device priority number. Note that multiple CAM blocks may source the device priority number (a multiple match condition), in which case the priority encoder generates a block identifier according to a predetermined tie resolution policy. For example, in one embodiment, the priority encoder generates a block identifier that identifies the lowest numbered one of the CAM blocks for which qualified match signals are asserted. In one embodiment, for example, the lowest numbered one of the CAM blocks is the CAM block having the lowest physical address for the memory address space spanned by the hash CAM blocks. Different priority encoding policies may be used in alternative embodiments.
Still referring to
Still referring to
Because all four hash CAM blocks 3191-3194 are initially empty, each hash CAM block will respond during a NFA operation by asserting its block flag and outputting the same fixed block priority value. Thus, the device priority logic (i.e., element 325 of
Although
Hash CAM Device having Shared Key/Hash Index Generation Circuitry
Hash CAM Block with Segmented Memory
The hash CAM block 470 includes a configuration register 473 that is similar to the configuration register 137 described in reference to
The entry size field within the entry type value (collectively designated an entry type/size value in
The entry size information within configuration register 473 is also provided to the output logic 475 to control the generation of a block flag signal 474, block priority value 472 and block index 476. The output logic 475 is coupled to the sense amplifier banks (SA) within the read/write circuit 481 to receive an entry segment 1381-1384 from each of the corresponding segments 4791-4794 of memory array 471. Depending on the operating mode selected by the entry type/size value within the configuration register 473, the entry segments 1381-1384 may be four distinct entries (x1 mode) that each span a single memory segment 479, two distinct entries (x2 mode) that each span a pair of memory segments, or a single entry that spans all four memory segments (x4 mode). The output logic 475 also receives the search key 210 from the assembler circuit 191, hash index 340 from the hash index generator 131, block select signal 332 from the block select logic 331, and NFA signal 212 from an instruction decoder (not shown in
In the x2 mode, gate 513 is selected to drive the block flag 474 via OR gate 517 and AND gate 519. AND gate 513 receives the output of OR gate 507 which receives outputs of AND gates 503 and 505. Each of AND gates 503 and 505 receives a respective pair of the segment flag signals, SF1/SF2 and SF3/SF4, so that an empty (or match) indication is indicated in the x2 mode only if SF1 and SF2 are both asserted or SF3 and SF4 are both asserted. In the x4 configuration, AND gate 515 is selected to drive the block flag 474 via OR gate 517 and AND gate 519. In the x4 mode, all four segment flags, SF1-SF4, are ANDed together in AND gates 503, 505 and 509 to generate the signal input to AND gate 515. Thus, in the x4 mode, all four segment flags must indicate an empty status in order for the block flag 474 to be asserted during a NFA operation, and all four segments flags must indicate a match condition in order for the block flag 474 to be asserted during a search operation. In an alternative embodiment, three of the four segment flags could be ignored in the x4 mode and one segment flag in each pair of segment flags could be ignored in the x2 mode.
The search priority logic 550 includes logic OR gates 541, 543, 545 and 547 to generate match-qualified priority values; comparator circuits C1,C2 and C3 to compare the match qualified priority values; multiplexers 549,551 and 553 to select a search priority value from among the match qualified priority values; and AND gates 555, 557, 559 and 561 to output the index select signals IS1-IS4 via multiplexer bank 570. Each of the OR gates 541,543,545,547 outputs a respective match qualified priority QPS1,QPS2,QPS3, QPS4 according to the state of the corresponding segment flags SF1-SF4. For example, if segment flag SF1 is high (indicating a match condition), OR gate 541 will output the PRIS1 value as the match-qualified priority value QPS1. If SF1 is low, indicating a mismatch condition, OR gate 541 will output a match disqualified priority value QPS1 in which all constituent bits are high (i.e., due to the inversion of the segment flag at the input to OR gate 541), which, in the embodiment of
Comparator C1 compares priority values QPS1 and QPS2 and generates a select signal 552 having a high logic state if priority value QPS1 indicates a higher priority (or equal priority) than priority value QPS2, and a low state if priority value QPS1 indicates a lower priority than priority value QPS2. That is, select signal 552 is high or low according to whether priority value QPS1 or QPS2, respectively, is the winner of the priority comparison in comparator C1. The select signal 552 is input to multiplexer 549 to select the C1 comparison winner (i.e., priority value QPS1 or QPS2) to be output to multiplexer 553 and comparator C3. Similarly comparator C2 compares the priority values QPS3 and QPS4 and generates a select signal 554 having a high or low state according to whether priority value QPS2 or QPS4 is the comparison winner. The select signal 554 is input to multiplexer 551 to select the C2 comparison winner (i.e., priority value QPS3 or QPS4) to be output to multiplexer 553 and comparator C3. Comparator C3 compares the priority numbers output by multiplexers 449 and 551 and generates a select signal 556 having a high or low state according to whether the priority value from multiplexer 449 or 551 is the comparison winner. The select signal 556 is provided to a select input of multiplexer 553 to select the C3 winner to be output as the search priority value 564 (SP). The select signals 552, 554 and 556 are also input to AND gates 555, 557, 559 and 561 to enable one of the AND gates to assert a high logic signal according to which priority value, QPS1, QPS2, QPS3 or QPS4, is the overall priority comparison winner. Thus, if select signals 552 and 556 are both high, then the output of AND gate 555 is high to indicate that QPS1 is the priority comparison winner. Similarly, if select signal 552 is low and 556 high, the output of AND gate 557 is high to indicate that QPS2 is the priority comparison winner; if select signal 556 is low and 554 high, the output of AND gate 559 is high to indicate that QPS3 is the priority winner; and if select signal 556 and 554 are both low, the output of AND gate 561 is high to indicate that QPS4 is the priority comparison winner. Thus, when in the x1 configuration, the memory segment that sources the highest priority match-qualified priority value will cause the corresponding index select signal, IS1-IS4, to be asserted.
NFA priority logic 571 is provided to generate the insert priority value 574. As discussed above, the insert priority value 574 may be compared with insert priority values from other hash CAM blocks during a NFA operation to select a hash CAM block for entry insertion. In the embodiment of
The partial fill bit 588 is generated by AND gate 573 according to the states of the segment flags SF1-SF4. Specifically, if any of the segment flags indicates an occupied segment (i.e., segment flag is low), the output of AND gate 573 goes low to produce a low partial fill bit 588. Conversely, if all the segment flags indicate unoccupied segments (i.e., all segments flags are high), the partial fill bit 588 is high. Thus, in the exemplary embodiment of
In the example of
In the example of
Although
Indirect Hashing using Binary CAM
In one embodiment, the hash index generator 131 generates a 16-bit hash index (a CRC value), the memory array contains 512 rows (i.e., addressable by a log2(512)=9 bit address), and the binary CAM stores 12 bits of the hash index, thus truncating the hash index by four, but not all seven extra bits. In an alternative embodiment, a ternary CAM may be used to store the full hash index together with mask information to mask out selected bits of the hash index. For example, a ternary CAM having a 16-bit storage width may be used to store a full 16-bit hash index, with any number of the hash index bits masked to produce, in effect, a smaller hash index. The hash index bits to be masked, if any, may be configured by a value stored within the configuration register of the hash CAM block. By this arrangement, different hash CAM blocks may be configured to use unmasked portions of a hash index to further reduce the likelihood of collisions in the CAM device. It should be noted that not all the CAM cells within such a ternary CAM device (i.e., ternary CAM device used to support indirect hashing) need to be ternary CAM cells. That is, each row within the ternary CAM device could include a number of binary CAM cells and a number of ternary CAM cells according to application needs.
In applications in which insertion policy favors insertion at partially filled rows, it may be desirable to increase the likelihood of a match within the binary CAM array 625 by masking selected bits of the hash index, effectively selecting a smaller hash index. In the embodiment of
In alternative embodiment, the hash index mask circuit 641 may be omitted and a ternary CAM array may be used in place of the binary CAM array 625. Mask values may then be stored with each hash index 340 loaded into the ternary CAM to effect the desired level of hash index masking. In another alternative embodiment, the hash index 340 is not masked for any of the entry size configurations (or to achieve truncation) so that the hash index mask circuit 641 may be omitted altogether.
Returning to
The binary CAM 601 also outputs a binary CAM index 608 (BCIN) and binary CAM flag 606 (BCF) to the output logic 609 where they are used to generate a block index 620 (BIN), block priority value 618 (BP) and block flag 616 (BF). The block index 620 is fed back to the address selector 605 to update selected address registers therein. It should be noted that, instead of outputting a decoded address to the memory array 477, a separate address decoder may be provided to receive an encoded address from binary CAM 601, and to decode the encoded address to activate the indicated word line within the memory array 477. In such an embodiment, the multiplexer 607 may receive the row address 602 output by the address selector (i.e., instead of the decoded row address 612) and the binary CAM index 608 output by the binary CAM 601 (i.e., instead of the binary CAM match signals). During an NFA or search operation, the binary CAM index 608 is selected to address the memory array 477, and during other operations (e.g., an insert operation), the row address 602 is selected to access the memory array 477.
In the embodiment of
During a load operation in the binary CAM 601, a hash index 340 is stored within a selected row of CAM cells within the binary CAM array 625, and validity values for each of the CAM rows are output on the match lines to indicate whether the corresponding row of CAM cells within the binary CAM array 625 are occupied. The binary CAM flag logic 631 generates the binary CAM flag 606 according to the state of the validity values. If the validity values indicate that all the rows of the binary CAM array 625 are occupied by valid hash indices, the binary CAM array 625 is full, and the binary CAM flag 606 is deasserted to indicate the full condition. The binary CAM priority encoder 633 also operates on the validity signals to generate a binary CAM index 608 that is indicative of a next free address within the binary CAM array 625. That is, the binary CAM priority encoder 633 generates an address of the highest priority location within the binary CAM array 625 indicated to be unoccupied by a corresponding validity signal.
In one embodiment, the binary CAM index 608 generated during a binary CAM load operation is buffered in a next free binary CAM address (NFBA) register 631 within the address selector 605. As discussed below, if no match is detected within the binary CAM array 625 during a subsequent NFA operation, the address value within the NFBA register 631 is selected by multiplexer 639 to be output as row address 602 and is selected by output logic 609 of
The address selector 605 additionally includes a partially filled row (PFR) register 633, a highest priority match (HPM) register 635 and an address counter 637 (CNTR), all of which are used to store address values. The partially filled row register 633 is used to store the block index 620 generating during a NFA operation that indexes a partially filled row (i.e., as opposed to a NFA operation in which no match is detected in the binary CAM 601). The HPM register 635 is used to store the block index 620 generated during a search operation that results in a match detection. Address counter 637 may be selected by multiplexer 639 to provide a sequence of ascending or descending indices to the binary CAM 601 and memory array 477, for example, to enable the binary CAM 601 and memory array 477 to be sequentially loaded with entries (e.g., during system startup). In alternative embodiments more or fewer address sources may be included within and/or selected by the address selector 605. For example, an error address register or test address generator may be included within the address selector 605 and selected by the multiplexer 639 to provide a sequence of error check addresses to the binary CAM 601 and/or memory array 477. In the embodiment of
Still referring to
The flag logic 645 includes an additional path for assertion of the block flag 616 in the event that the binary CAM flag 606 is not asserted during a NFA operation, but the binary CAM is not full. That is, if the binary CAM flag 606 is not asserted during the NFA operation then no matching index was located within the binary CAM; a result indicating that the hash CAM block is not conflicted. Accordingly, so long as the binary CAM is not full, the new hash index (i.e., the storage index generated in response to the entry candidate) may be stored in the next free address of the binary CAM and the entry candidate may be stored in the corresponding row of the memory. In the embodiment of
The fill counter 585 within priority logic 670 is incremented in response to a binary CAM load (indicated by a BCWR signal) and decremented in response a binary CAM delete (indicated by a BCDEL signal). By this arrangement, the fill counter 585 indicates the number of rows within the memory array which are at least partially filled. As discussed above, different fill measures may be used in alternative embodiments, and the fill count may be omitted from the insert priority value 672 altogether.
Still referring to
If a match is not detected within the binary CAM (717), then at 721 a buffered binary CAM flag (stored during the most recent binary CAM load operation) is inspected to determine whether the binary CAM is full. If the binary CAM is full, the block flag is deasserted at 727. If the binary CAM is not full, then at 725 the binary CAM fill count and a logic high partial fill bit (indicated by the summation of 200 hex and the fill count in the example of
Overflow CAM Having Search-Based NFA Function
The CAM array 801 can be configured into different width by depth configurations by programming an entry size value into the configuration register 819. The entry size information is output as a set of one or more signals 840 (CFG) to configuration dependent circuit blocks within the overflow CAM block 800. In the exemplary embodiment shown in
When an entry is loaded into the CAM array 801, the address logic 811 decodes an address received via bus 230 to assert an indicated one of the word lines 830 (WL1-WLY), and the read/write circuit 815 drives an entry onto array bit lines 834 of the appropriate entry segment or segments (as discussed above, a segment address portion of the incoming address may be used in conjunction with the configuration value to select one or more entry segments to be written). A priority value may be loaded into the priority index table 803 (e.g., by the operation of read/write circuit 815 to drive a priority value onto priority bit lines 836) concurrently with the loading of the corresponding entry within the CAM array 801 or at a different time. In the x1 configuration, for example, entries stored within segments S1-S4 of a given row of the CAM array 801 correspond to priority values stored within priority storage circuits P1-P4 in the priority index table 803. In one embodiment, the priority values used in the x1, x2 and x4 configurations are the same size (i.e., have the same number of constituent bits). Consequently, in the x1 embodiment, each of the four priority storage circuits P1-P4 is used to store a priority value that corresponds to an entry in a corresponding one of entry segments S1-S4, while in the x2 configuration, only two of the priority storage circuits are used to store priority values (i.e., to correspond to respective entries that span two entry segments), and in the x4 configuration, only one of the priority storage circuits is used to store a priority value (i.e., to indicate the priority of a corresponding x4 entry). In the x2 and x4 configurations, the unused priority circuits may be disabled or loaded with null data (e.g., minimum priority values). In alternative embodiments, differently sized priority values may be used for different CAM array configurations, and all or a portion of one priority storage circuit may be concatenated with another priority storage circuit to enable storage of larger sized priority values.
The priority values stored within the priority index table 803 indicate the relative priorities of corresponding entries within the CAM array 801 and may be assigned in ascending priority order or descending priority order. During a search operation, search key 210 is simultaneously compared with all the entries within the CAM array 801 to generate a set of match signals 8101-810Y, each indicating whether an entry or entries within a corresponding row of the CAM array 801 matches the search key 210. The priority values within the priority index table 803 that correspond to key-matching entries within the CAM array 801 (i.e., match-qualified priority values) are compared with one another to determine a highest priority match-qualified priority value. The highest priority match-qualified priority value is output from the priority index table 803 as a search priority value 832 (SP) and is received by the priority select logic 809. The priority select logic 809 selects, according to the state of NFA signal 212, either the search priority value 832 or an insert priority value to be output as the block priority value 822. More specifically, during an NFA operation, when the NFA signal 212 is high, the priority select logic 809 outputs an insert priority value, and during a search operation, when the NFA signal is low, the priority select logic 809 outputs the search priority value 832.
The priority index table additionally outputs a set of qualified match signals 812 to the priority encoder 805 and match flag logic 807. Each of the qualified match signals corresponds to a row of the priority index table 803 (and therefore to a row of CAM array 801) and is asserted if a match qualified priority value equal to the search priority value 832 is stored in the priority index table row.
Each of the Y tag logic circuits 847 receives a respective match signal 810 from a corresponding row of the CAM array. In one embodiment, each of the match signals 810 includes five component match signals MT and M1-M4, that correspond to the tag segment and entry segments S1-S4, respectively. Each of the tag logic circuits 8471-847Y outputs a respective set of four tag match signals, TM1-TM4, with each of the tag match signals being asserted if (1) a tag value stored in the tag segment matched a class code value associated with the search key (i.e., the class code value (CC) discussed above in reference to FIG. 17), and (2) an entry stored in the corresponding entry segment (or, in the x2 and x4 configurations, in a group of two or four entry segments) matched the search key. The entry size information, CFG 840, is input to the tag logic circuits 8471-847Y to qualify the detection of a match condition.
In the embodiment of
The operation of priority index table 900 can be illustrated with an example shown in FIG. 55. In this example, priority index table 900 comprises a 2×4 matrix of rows and columns. For other embodiments, any numbers of rows and columns can be used. Row one stores priority number 0110 having the decimal equivalent of the number 6, and row two stores priority number 0101 having the decimal equivalent of the number 5. For this example, the corresponding row of the CAM array contains segment entries that result in assertion of tag match lines TM1 and TM2. Also, for this example, the priority numbers are stored in ascending priority order such that 0101 is the more significant (i.e., “higher priority”) priority number between 0101 and 0110.
Compare circuits 9061,1-9064,2 determine that 0101 is the more significant priority value, and cause PM12 to be asserted as follows. The most significant bit CP14 is resolved first. When any memory element 871 stores a logic zero and the corresponding match line segment 910 is asserted, the corresponding priority signal line 908 is discharged. Thus, each of compare circuits 9064,2 and 9064,1 discharge signal line 9084 such that CP14 is a logic zero. Additionally, compare circuit 9064,2 compares the state of priority signal line 9084 with the priority number bit stored in 8714,2, and determines that both have the same logic state. This causes compare circuit 9064,2 not to affect the logical state of match line segment 9103,2 such that match line segment 9103,2 has the same logic state as match line segment 9104,2 (TM12). Similarly, compare circuit 9064,1 compares the state of priority signal line 9084 with the priority number bit stored in 8714,1 and determines that both have the same state. This causes compare circuit 9064,1 not to affect the logical state of match line segment 9103,1 such that match line segment 9103,1 has the same logic state as match line segment 9104,1 (TM11).
The next most significant bit CP13 is then resolved. Memory elements 871 that store a logic one do not discharge their corresponding priority signal lines 908. Since memory elements 8713,2 and 8713,1 both store logic one states, signal line 9083 remains pre-charged such that CP13 is a logic one. Additionally, compare circuit 9063,2 compares the state of priority signal line 9083 with the priority number bit stored in 8713,2 and determines that both have the same logic state. This causes compare circuit 9063,2 not to affect the logical state of match line segment 9102,2 such that match line segment 9102,2 has the same logic state as match line segment 9103,2. Similarly, compare circuit 9063,1 compares the state of priority signal line 9083 with the priority number bit stored in 8713,1 and determines that both have the same logic state. This causes compare circuit 9063,1 to not affect the logical state of match line segment 9102,1 such that match line segment 9102,1 has the same logic state as match line segment 9103,1.
CP12 is resolved next. Since memory element 8712,2 stores a logic zero and match line segment 9102,2 is asserted, compare circuit 9062,2 discharges priority signal line 9082. This causes CP12 to be a logic zero. Additionally, compare circuit 9062,2 compares the logic zero state of priority signal line 9082 with the logic zero stored in 8712,2 and allows match line segment 9101,2 to have the same state as match line segment 9102,2. Compare circuit 9062,1, however, compares the logic zero on priority signal line 9082 with the logic one stored in memory element 8712,1, and de-asserts match line segment 9101,1. When a match line segment is de-asserted, all subsequent compare circuits for that row will de-assert the remaining match line segments of the row such that the corresponding prioritized match signal PM11 will be de-asserted. When the prioritized match signal is de-asserted for a particular segment, this indicates that the most significant priority number is not stored in that segment. Additionally, when the remaining match line segments are de-asserted for a row, the compare circuits for that row do not discharge the remaining priority signal lines regardless of the logic states stored in the corresponding memory elements of that row. For example, compare circuit 9061,1 does not discharge priority signal line 9081 even though memory element 8711,1 stores a logic zero. Additionally, isolation circuits 9044,1, 90431, and 9042,1 isolate the de-asserted match line segment 9101,1 from match line segment 9104,1, 9103,1, and 9102,1 such that CP14, CP13, and CP12 are not affected by the de-assertion of match line segment 9101,1.
Lastly, the least significant bit CP11 is resolved. Compare circuit 9061,2 alone determines CP11 since compare circuit 9061,1 cannot discharge priority signal line 9081. Since memory element 8711,2 stores a logic one and match line segment 9101,2 is asserted, compare circuit 9061,2 leaves priority signal line 9081 pre-charged, and CP11 is a logic one. Additionally, compare circuit 9061,2 allows prioritized match signal PM12 to have the same state as match line segment 9101,2. Since match line segment 9101,2 is asserted, PM12 will be asserted indicating that the most significant priority number is stored in that row.
Thus, when the priority comparison is completed, bits CP14-CP11 indicate that the most significant priority number stored in the priority index table is 0101, and prioritized match signal PM12 is asserted to signal that 0101 is stored in row two.
For the example described above with respect to
Any circuits may be used for compare circuits 906 and/or isolation circuits 904 to implement the priority comparison illustrated above. Table 2 shows one example of a truth table for implementing each compare circuit 906, where X (column) and Y (row) are any integers. Other truth tables may be used (and corresponding logic generated accordingly) including those that logically complement one of more or the signals indicated in Table 2. Any logic or circuitry may be used to implement the truth table of Table 2.
Compare circuit 933 includes inverter 944, transistors 936 and 938 connected in series between priority signal line 908 and ground, and transistors 940 and 942 connected in series between match line segment 910i-1 and ground. N-channel transistor 936 has its drain coupled to signal line 908, its gate coupled to match line segment 910i, and its source coupled to the drain of n-channel transistor 938. Transistor 938 has its gate coupled to receive the logical complement of the priority number bit (/D) stored in memory element 871, and its source coupled to ground. N-channel transistor 940 has its drain coupled to match line segment 910i-1, its gate coupled to signal line 908 via inverter 944, and its source coupled to the drain of N-channel transistor 942. Transistor 942 has its gate coupled to receive the priority number bit (D) stored in memory element 871, and its source coupled to ground. Any of transistors 936, 938, 940, and 942 can be replaced with other types of transistors and the logic adjusted accordingly.
Isolation circuit 931 includes inverters 932 and 934. For alternative embodiments, only one inverter may be used and the logic of the next compare circuit adjusted accordingly. For other embodiments, other isolation circuits such as one or more AND, OR, or XOR logic gates or pass gates may be used.
Reflecting on the operation of priority cell 930, it can be seen that at least two principal functions are performed. First, the compare circuit 933 pulls down the column priority signal line 908 if (1) the incoming match line segment 910, is high (thereby indicating that priority cell 930 is enabled to participate in the bitwise priority comparison with other priority cells in the same column), and (2) the priority number bit is the lowest valued priority number bit in the column (i.e., the priority number bit, D, is a 0). Second, the priority cell 930 selectively enables or disables the next less significant priority cell from affecting the bitwise priority comparison for its column by setting the state of the outgoing match line segment 910i-1. Specifically, the priority cell 930 pulls down the outgoing match line segment 919i-1 to disable the next less significant priority cell from affecting the bitwise priority comparison for the next less significant column if (1) the incoming match line segment 910i is low (i.e., causing 910i-1 to be pulled down via isolation circuit 931) or (2) the column priority signal line 908 settles to a low state and the priority number bit, D, is a 1 (i.e., priority cell 930 is a loser of the column priority comparison). In a priority table having Y rows (priority cell 930 being at column i, now j), the above described functions may be described by the following Boolean expressions:
Substituting (1) for CP1i in expression (2) yields:
/910i-1j=/910ij+[Dij*{(910i,1)+(910i,2*/Di,2)+. . . +(9101,Y*/Di,Y)}]
Thus, if the incoming match line segment 910i is high and the priority number bit, D, is a 1, the outgoing match line segment 910i-1 may not settle to its final state until all (or a significant number) of the priority cells within the same column have completed their comparisons of priority number bits and input match line segment states. Because of this potentially long settling time, it becomes possible for the outgoing match line segment 910i-1 to temporarily be high, before ultimately being pulled low. Consequently, the next less significant priority cell within may be enabled to temporarily pull the next less significant column priority signal line low (i.e., CP1i-1=0) before finally being disabled by the low going match line segment 910i-1. While an array of the priority cells 930 is self-correcting and will ultimately output the correct set of priority number bits as the column priority value and will assert the proper prioritized match signals, the temporary transition of one or more priority cells to an incorrect state requires time to correct. That is, transistor states require time to be reversed, and signal lines require time to charge/discharge, thereby slowing the overall generation of prioritized match signals and determination of a column priority number.
In one embodiment, TR is a fixed value that corresponds to a time required for a column of priority cells to resolve the state of the column priority signal line (e.g., resolution time plus a tolerance value). Alternatively, TR may be a programmable value within the CAM device (e.g., stored in the configuration register 819 of
A predetermined time after ripple enable signal RE1 has been asserted, TC, the priority number comparison is completed and all the ripple enable signals may be deasserted in preparation for the next priority number comparison. In the example of
Referring again to
If the entry size information 840 indicates a x4 configuration, the output of AND gate 952 is selected to drive each of the tag match signals TM1-TM4. AND gate 952 performs a logical AND of the outputs of all the AND gates 9511-9514 and therefore outputs a logic high signal only if all the incoming segment match signals (MT and M1-M4) are high. Thus, in the x4 condition, all the tag match signals TM1-TM4 are asserted (i.e., to a high logic state in this example) if (1) the stored tag matches the class code associated with the search key, and (2) a x4 entry stored in segments 1-4 matches the search key (as indicated by assertion of signals M1-M4). If the stored tag does not match the class code, or any of the entry segment match signals indicate a mismatch condition, all the tag match signals TM1-TM4 are deasserted to indicate a mismatch.
If the entry size information 840 indicates a x2 configuration, the output of AND gate 953 is selected to drive tag match signals TM1 and TM2, and the output of AND gate 954 is selected to drive tag match signals TM3 and TM4. AND gate 953 performs a logical AND of the outputs of AND gates 9511 and 9512 and therefore outputs a logic high signal if (1) the stored tag matches the class code associated with the search key, and (2) a x2 entry stored in segments 1 and 2 matches the search key (as indicated by assertion of signals M1 and M2). If the stored tag does not match the class code or if either of entry segment match signals M1 and M2 indicate a mismatch condition, tag match signals TM1 and TM2 are both deasserted to indicate a mismatch. AND gate 954 performs a logic AND of the outputs of AND gates 9513 and 9514 and therefore outputs a logic high signal if (1) the stored tag matches the class code associated with the search key, and (2) a x2 entry stored in segments 3 and 4 matches the search key (as indicated by assertion of signals M3 and M4). If the stored tag does not match the class code or if either of entry segment match signals M3 and M4 indicate a mismatch condition, tag match signals TM3 and TM4 are both deasseerted to indicate a mismatch.
Note that for all entry size configurations, the tag match signals TM1-TM4 are deasserted if the tag segment match signal is deasserted (indicating a mismatch between the stored tag and class code for the search value). In alternative embodiments, the tag segment may be used to qualify the entry segment match signals for only a set of one or more of the entry size configurations, with the set of configurations being fixed or programmable (e.g., by a configuration setting within register 819 of FIG. 52). In another alternative embodiment, the match the tag segment may be omitted from the CAM array 801 and the tag logic 847 omitted from the priority index table 803.
Still referring to
Referring again to
Any logic circuit that produces the above Boolean result may be used to implement the block flag logic, and, in alternative embodiments, different Boolean expressions may be used. For example, in an embodiment in which qualified match signals QM2 and QM4 are ignored in x2 mode and qualified match signals QM2, QM3 and QM4 are ignored in x4 mode, the block flag signal may be asserted in accordance with the following Boolean expression:
Still referring to
Each of the segment priority encoders 9591-959Y also receives a respective set of qualified match signals QM1-QM4 and performs an encoding operation to generate a respective prioritized segment address PSA. In one embodiment, if two or more of qualified match signals QM1-QM4 are high, the segment priority encoder 959 generates a prioritized segment address that corresponds to the lowest numbered one of the qualified match signal (i.e., the qualified match signal that corresponds to the CAM array segment having the lowest physical address as compared with other segments within the same row). By this arrangement, the prioritized segment address generated in response to a match detection in the x4 configuration (i.e., all qualified match signals asserted) will indicate segment 1 (e.g., PSA=00 binary), and the prioritized segment address generated in response to a match detection in the x2 condition (at least one pair of match signals asserted) will indicate segment 1 or segment 3 (e.g., PSA=00 or 10), as the case may be. Also, in the event of multiple matches within a single row in either the x1 or x2 configuration, the address of the lowest numbered segment will be output as the prioritized segment address. In alternative embodiments, different segment prioritizing policies may be used to generate prioritized segment address.
The multiplexer 958 receives Y prioritized segment addresses (PSA1-PSAY) from the segment priority encoders 9591-949Y and selects, according to the row index 962, one of the prioritized segment address to be output as a segment index 963 (SIN). Thus, the segment index 963 is the prioritized segment address that corresponds to the row that yielded the row index 962. Together the row index 962 and segment index 963 form the block index 826 for the overflow CAM block.
Referring again to
Referring to
During an NFA operation, the NFA signal 212 is high, enabling AND gate 969 to select, according to the state of the block flag 824, either the entry index 828 or the next free overflow CAM address 968 (stored within storage element 965) to be output as the block index 826. More specifically, if the block flag is high during a NFA operation (i.e., indicating an unoccupied entry segment(s) within a row containing a tag that matches the class code associated with the entry candidate) the inversion at the block flag input to the AND gate 969 causes the output of AND gate 969 to be low and therefore to select the entry index 828 (i.e., the index of an empty entry segment within the CAM array) to be output as the block index 826. If the block flag is low during a search operation, then no match was detected (indicating that no row contained both a tag that matched the class code and an empty entry segment), and the output of the logic AND gate 969 is high to select the next free overflow CAM address 968 to be output as the block index 826. Thus, during an NFA operation, an entry index 828 is output for a partially (or completely) empty row having a tag that matches the class code associated with the entry candidate, and the next free overflow CAM address 968 is output if there is no such row.
System Structure and Operation
The host processor 975 executes program code stored within program store 979 (which may include one or more semiconductor storage devices or other storage media) and issues addresses, comparands, and instructions to the CAM device 977 via the address, data and instruction buses, respectively (i.e., ABUS 230, DBUS 140 and IBUS 200), and receives status and other information from the CAM device 1701 via a result bus (RBUS 990). In particular, the host processor 975 issues instructions to program or select the entry types, key masks, hash function selections, entry sizes, compare modes, fill policies and other programmable or selectable features of one or more CAM blocks within the CAM device 977, as discussed above. In the embodiment of
In alternative embodiments, one or more of the buses (e.g., ABUS, DBUS, IBUS, or RBUS) may be omitted and the corresponding information time multiplexed onto another of the buses. Further, the CAM device 977 and host processor 975 may be implemented in distinct integrated circuits (ICs) and packaged in distinct IC packages, or in a single IC (e.g., in an ASIC, system-on-chip, etc.), or in an IC package that includes multiple ICs (e.g., a multi-chip package, paper thin package, etc.). Also, the system 980 may include multiple CAM devices 977 each programmed with a respective set of configuration values. For example, in one embodiment, system 980 includes multiple CAM devices according to hash CAM device 190 of
Numerous functions described as being implemented within the CAM devices of
In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
Claims
1. A method of operation within an integrated circuit device, the method comprising:
- generating an index based on a search value;
- determining whether constituent bits of the search value, including bits thereof used to generate the index, match corresponding bits of a data value stored at a memory location indicated by the index; and
- outputting, from the integrated circuit device, the indent and an indication of whether the constituent bits of the search value match the corresponding bits of the data value.
2. The method of claim 1 wherein generating the index based on the search value comprises selecting a portion of the search value, and generating the index based on the selected portion of the search value.
3. The method of claim 2 wherein selecting the portion of the search value comprises selecting the portion of the search value in accordance with a configuration value stored within the integrated circuit device.
4. The method of claim 1 wherein accenting an index based on the search value comprises:
- assembling dispersed fields of bits within the march value to form a search key; and generating the index based on the search key.
5. The method of claim 4 further comprising masking selected bits within the search key prior to generating the index.
6. The method of claim 5 wherein masking selected bits within the search key comprises masking bits within the search key in accordance with a configuration value within the integrated circuit device.
7. The method of claim 4 wherein assembling dispersed fields of bits within the search value to form the search key comprises assembling the dispersed fields of bits into a contiguous set of bits in accordance with a configuration value within the integrated circuit device.
8. The method of claim 7 wherein the configuration value specifies a data format of the search value.
9. The method of claim 1 wherein generating the index based on the search value comprises generating a hash index based on the search value, the hash index having fewer constituent bits then the search value.
10. The method of claim 9 wherein generating the hash index comprises generating a cyclic redundancy check (CRC) value.
11. The method of claim 1 wherein determining whether the search value matches the data, value comprises comparing the search value with the data value to generate a match signal that indicates whether the search value matches the data value.
12. The method of claim 11 wherein outputting the indication of whether the search value matches the data value comprises outputting the match signal.
13. The method of claim 11 wherein comparing the search value with the data value comprises comparing a selected potion of the search value with a selected portion of the data value, the selected portions of the search value and data value being indicated by a mask value.
14. The method of claim 13 further comprising retrieving the mask value from the memory, location indicated by the index.
15. The method of claim 13 further comprising decoding an encoded value to generate the mask value.
16. The method of claim 15 fuller comprising retrieving the encoded value from the memory location indicated by the index.
17. The method of claim 11 wherein comparing the search value with the data value comprises determining whether the search value is greater than the data value and wherein generating the match signal that indicates whether the search value matches the data value comprises generating a match signal to indicate that the search value matches the data value if the search value is not greater then the data value.
18. The method of claim 11 wherein comparing the search value with the data value comprises determining whether the search value is less then the data value and wherein generating the match signal then indicates whether the search value matches the data value comprises generating a match signal to indicate that the search value matches the data value if the search value is not less then the data value.
19. The method of claim 11 wherein comparing the search value with the data value comprises performing either a range comparison or a match comparison according to a configuration value within she integrated circuit device, and wherein performing a range comparison comprises determining whether the search value is greater than the date value.
20. The method of claim 1 wherein generating an index based on a search value comprises:
- generating a plurality of hash values based on the search value, each hub value having fewer constituent bits than the search value; and
- selecting one of the hash values to be the index.
21. The method of claim 20 wherein selecting one of the hash values to be the index comprises selecting the one of the hash values in accordance with a configuration value within the integrated circuit device.
22. The method of claim 1 further comprising:
- retrieving a priority value from the memory location indicated by the index; and
- outputting the priority value from the integrated circuit device.
23. A method of operation within an integrated circuit device, the method comprising:
- receiving a search value;
- generating an index based on a selected bits of the search value;
- determining whether constituent bits of the search value, including the selected bits match corresponding bits of a data value stated at a memory location indicated by the index; and
- selecting the selected bits of the search value in accordance with a configuration value stored within the integrated circuit device.
24. A method of operation within an integrated circuit device, the method comprising:
- receiving a search value;
- generating an index based on a selected bits of the search value;
- determining whether constituent bits of the search value, including the selected bits match corresponding bits of a data value stored at a memory location indicated by the index; and
- wherein generating an index based on selected bits of the search value comprises: assembling dispersed fields of bits within the search value to form a search key; and generating the index based on the search key.
25. The method of claim 24 further comprising masking bits within the search key prior to generating the index.
26. The method of claim 25 wherein masking bits within the search key comprises masking bits within the search key in accordance with a configuration value within the integrated circuit device.
27. The method of claim 24 wherein assembling dispersed fields of bits within the search value to form the search key comprises assembling the dispersed fields of bits into a contiguous set of bite in accordance with a configuration value within the integrated circuit device.
28. The method of claim 23 wherein generating the index based on selected bits of the search value comprises generating a hash index based on the selected bits of the search value, the hash index having fewer constituent bits than the search value.
29. The method of claim 28 wherein generating the hash index comprise generating a cyclic redundancy check (CRC) value.
30. A method of operation within an integrated circuit device, the method comprising:
- generating an index based on a search value;
- generating an indication of whether a first portion of the search value, including constituent bits of the search value used to generate the index, matches a selected portion of a data value stored at a memory location indicated by the index; and
- wherein generating the index based on the match value comprises selecting portion of the first portion of the search value, and generating the index based on the selected portion of the first portion of the search value, and
- wherein selecting the portion of the first portion of the search value comprises selecting the portion of the first portion of the search value in accordance with a configuration value stored within the integrated circuit device.
31. A method of operation within an integrated circuit device, the method comprising:
- generating an index based on a search value;
- generating an indication of whether a first portion of the starch value, including constituent bits of the search value used to generate the index, matches a selected portion of a data value stored at a memory location indicated by the index; and
- wherein generating an index based on the search value comprises: assembling dispersed fields of bits within the search value to form a search key; and generating the index based on the search key.
32. The method of claim 31 further comprising masking selected bits within the search key prior to generating the index, the selected bits being selected in accordance with a configuration value within the integrated circuit device.
33. The method of claim 30 wherein generating an indication of whether a first portion of the search value matches a selected portion of a data value stored at a memory location indicated by the index comprises:
- retrieving the data value from the memory location indicated by the index; and
- comparing the first portion of the search value with the selected portion of the data value to generate a match signal that indicates whether the search value matches the data value.
34. A method of operation within an integrated circuit device, the method of comprising:
- generating an index based on a search value;
- generating an indication of whether a first portion of the search value, including constituent bits of the search value used to generate the index, matches a selected portion of a data value stored at a memory location indicated by the index;
- retrieving mask information from the memory location indicated by the index, the mask information indicating the selected portion of the data valve; and
- wherein generating the indication of whether the first portion of the search value matches the selected portion of the data value stored at the memory location indicated by the index comprises: retrieving the data value from the memory location indicated by the index; and comparing the first portion of the search value with the selected portion of the data value to generate the match signal that indicates whether the search value matches the data value.
35. The method of claim 34 further comprising decoding an encoded value included within the mask information to generate a decoded mask value, the mask value indicating the selected portion of the data value.
36. A method of operation within an integrated circuit device the method comprising:
- generating a search index based on a search value; and
- identifying, within a content addressable memory (CAM), one of a plurality of stored indices that matches the search index; and
- determining whether the search value matches a data value stored at a first location within a data memory, the first location corresponding to a location of the one of the plurality of indices.
37. The method of claim 36 wherein generating the search index based on the search value comprises selecting a portion of the search value, and generating the search index based on the selected portion of the search value.
38. The method of claim 37 wherein selecting the portion of the search value comprises selecting the portion of the search value in accordance with a configuration value within the integrated circuit device.
39. The method of claim 36 wherein generating the search index based on the search value comprises generating a search index having fewer constituent bits than the search value.
40. The method of claim 36 wherein generating the search index comprise generating a cyclic redundancy check (CRC) value.
41. The method of claim 36 wherein identifying, within the CAM, one of a plurality of stored indices that matches the search index comprises comparing the search index with each of the plurality of stored indices.
42. The method of claim 41 wherein comparing the search index with each of the plurality of stored indices comprises simultaneously comparing the search index with each of the plurality of stored indices.
43. The method of claim 41 wherein identifying one of a plurality of stored indices that matches the search index further comprises generating a plurality of match signals, each match signal indicating whether a respective one of the stored indices matches the search index.
44. The method of claim 36 wherein determining whether the search value matches a data value stored at a first location within a data memory comprises:
- retrieving the data value from the first location within the memory; and
- comparing the search value with the data value.
45. The method of claim 44 wherein retrieving the data value from the first location within the memory comprises:
- generating a row address indication that corresponds to the one of the plurality of stored indices that matches the search index; and
- retrieving the data value from a location within the memory indicated by the row address indication.
46. The method of claim 45 wherein generating the row address indication comprises generating a plurality of match signals that each indicate whether a respective one of the stored indices matches the search index.
47. The method of claim 46 wherein generating the row address indication further comprises encoding the plurality of match signals into a row address.
48. The method of claim 47 wherein encoding the plurality of match signals into a row address comprises retrieving the row address from a lookup table storage location indicated by the plurality of match signals.
49. A method of operation within an integrated circuit device, the method comprising:
- converting a search value into a search index having fewer constituent bits than the search valve;
- identifying, within a content addressable memory (CAM), one of a plurality of stored indices that matches the search index; and
- outputting a data value from a first location within a data memory, the first location corresponding to a location within the CAM of the one of the plurality of indices.
50. The method of claim 49 further comparing determining whether the search value matches the data value.
51. The method of claim 50 further comprising generating a match signal that indicates whether the search value matches the data value.
52. The method of claim 49 wherein converting a match value into a search index comprises converting a selected portion of the search value into a search index.
53. The method of claim 49 wherein converting a search value into a search index comprises generating a hash index based on the search value.
54. The method of claim 53 wherein generating a hash index comprises generating a cyclic redundancy check (CRC) value.
55. The method of claim 49 wherein identifying within the CAM, one of a plurality of stored indices that matches the search index comprises comparing the search index with each of the plurality of stored indices.
56. The method of claim 55 wherein comparing the search index with each of the plurality of stored indices comprises simultaneously comparing the search index with each of the plurality of stored indices.
57. The method of claim 55 wherein identifying, within a content addressable memory (CAM), one of a plurality of stored indices that matches the search index further comprises generating a plurality of match signals, each match signal indicating whether a respective one of the stored indices matches the search index.
58. The method of claim 49 wherein outputting the data value from the first location within the data memory comprises:
- generating a new address indication that corresponds to the one of the plurality of stored indices that matches the search index; and
- retrieving the data value from a location within the data memory indicated by the row address indication.
59. The method of claim 58 wherein generating the row address indication comprises generating a plurality of match signals that each indicate whether a respective one of the stored indices matches the search index.
60. The method of claim 59 wherein generating the row address indication further comprises encoding the plurality of match signals into a row address.
61. A method of operation within an integrated circuit device, the method comprising:
- generating a plurality of indices based on a search value;
- selecting, according to a select value, one of the plurality of indices; and
- determining whether the search value matches a data value stored at a memory location indicated by the one of the plurality of indices.
62. The method of claim 61 wherein generating a plurality of indices based on a search value comprises selecting a portion of the search value, and generating each of the plurality of indices based on the selected portion of the search value.
63. The method of claim 62 wherein selecting the portion of the search value comprises selecting the portion of the search value in accordance with a configuration value stored within the integrated circuit device.
64. The method of claim 62 wherein generating each of the plurality of indices based on the search value comprises:
- assembling dispersed fields of bits within the search value to form a search key; and
- generating each of the plurality of indices based on the search key.
65. The method of claim 64 further comprising masking selected bits within the search key prior to generating the plurality of indices.
66. The method of claim 65 wherein masking selected bits within the search key comprises masking bits within the search key in accordance with a configuration value within the integrated circuit device.
67. The method of claim 61 wherein selecting one of the plurality of indices comprises selecting one of the plurality of indices in accordance with a configuration value within the integrated circuit device.
68. The method of claim 61 wherein generating a plurality of indices based on a search value comprises generating a plurality of different indices based on the search value.
69. The method of claim 68 wherein generating a plurality of plurality of different indices comprises inputting at least a portion of the search value to a plurality of hash function circuits, each hash function circuit being adapted to generate a respective hash index based on a hash function that is different from the others of the hash function circuits.
70. The method of claim 61 wherein determining whether the search value matches a data value stored at a memory location indicated by the one of the plurality of indices comprises comparing the search value with the data value and generating a match signal the indicates whether the search value matches the data value.
71. The method of claim 70 wherein comparing the search value with the date value comprises comparing a selected portion of the search value with a selected portion of the data value, the selected portions of the search values and data value being indicated by a mask value.
72. The method of claim 71 further comprising retrieving the mask value from the memory location indicated by the one of the plurality of indices.
73. A method of operation within an integrated circuit device, the method comprising:
- generating a plurality of indices based on a search value;
- retrieving a plurality of data values from a plurality of memories, each data value being retrieved from a respective one of the memories at a location indicated by a respective one of the plurality of indices;
- comparing the search value to each of the plurality of data values to identity one of the data values that matches the search value; and
- generating a value that identifies the respective one of the memories from which the one of the data values that matches the search value was retrieved.
74. The method of claim 73 wherein generating a plurality of indices based on a search value comprises generating a plurality of hash indices based on at least a portion of the search value, each of the hash indices having fewer constituent bits than the search value.
75. The method of claim 74 wherein generating the plurality of hash indices comprises generating a plurality of cyclic redundancy check (CRC) values.
76. The method of claim 73 wherein comparing the search value to each of the plurality of data values comprises comparing the search value with a selected portion of each of the data values, the selected portion of each of the data values being indicated by a respective mask value.
77. The method of claim 76 further comprising retrieving the respective mask value from a respective one of the memories at a location indicated by a respective one of the plurality of indices.
78. The method of claim 73 wherein retrieving a plurality of data values from a plurality of memories comprises retrieving a first data value from a first one of the plurality of memories, and retrieving a second data value from a second one of the plurality of memories, the second one of the plurality of memories having a different storage capacity than the first one of the plurality of memories.
79. A method of operation within an integrated circuit device, the method comprising:
- receiving a search value and a corresponding search code;
- comparing the search code to a plurality of configuration values, each of the configuration values corresponding to a respective one of a plurality of data memories within the integrated circuit device;
- generating a plurality of indices based on the search value;
- retrieving a plurality of data value from the plurality of data memories, each data value being retrieved from a respective one of the data memories at a location indicated by a respective one of the indices; and
- generating, for each of the plurality of data memories, a respective match signal having a first state if the search value matches the data value retrieved from the data memory and if the search code matches the configuration value that corresponds to the data memory.
80. The method of claim 79 wherein receiving a search code comprises receiving a search code that indicates a formatting of the corresponding search value.
81. The method of claim 79 wherein receiving a search code comprises receiving a search code that indicates positions of maskable bits within the corresponding search value.
82. The method of claim 79 wherein generating a match signal having a first state if the search value matches the data value retrieved from the data memory and if the search code matches the configuration value that corresponds to the data memory comprises:
- comparing a selected portion of the search value and a selected portion of the data value; and
- generating a match signal having a first state if the selected portion of the search signal matches the selected portion of the data value and if the search code matches the configuration value.
83. The method of claim 79 further comprising retrieving a plurality of priority values from the plurality of data memories, each priority value being retrieved from a respective one of the data memories at a location indicated by a respective one of the indices.
84. The method of claim 79 further comprising generating an identifier based on the plurality of priority values and the match signals generated for the plurality of data memories, the identifier indicating one of the plurality of date memories.
85. The method of claim 84 wherein generating an identifier that indicates one of the plurality of data memories comprises generating an identifier that indicates a data memory of the plurality of data memories that contains a highest priority one of the plurality of priority values and for which the respective match signal has the first state.
86. A method of operation within an integrated circuit device, the method comprising:
- generating an index based on an input value;
- retrieving a first value from a location, indicated by the index, within a first memory;
- comparing the first value to the input value to generate a first match signal that indicates whether the input value matches the first value; and
- comparing the input value simultaneously to each of a plurality of values stored in a second memory to generate a second match signal that indicates whether the input value matches one of the plurality of values stored in the second memory.
87. The method of claim 86 wherein comparing the input value simultaneously to each of a plurality of values stored in the second memory comprises comparing the input value to a plurality of values stored in an array of content addressable memory (CAM) cells, each CAM cell including a storage element end a compare circuit.
88. The method of claim 86 further comprising:
- outputting a first priority value from the location within the first memory;
- outputting a second priority value from the second memory; and
- comparing the first priority value and the second priority value in accordance with the states of the first and second match signals to determine a highest priority one of the priority values.
89. The method of claim 88 wherein comparing the first priority value and the second priority value in accordance with the states of the first and second match signals to determine a highest priority one of the priority values comprises determining the first priority value to be the highest priority value if the first match signal is asserted and the first priority value indicates a higher priority than the second priority value.
90. The method of claim 86 wherein generating an index based on an input value comprises generating an index having fewer constituent bits than the input value.
91. The method of claim 86 wherein generating the index based on the search value comprises selecting a portion of the search value, and generating the index based on the selected portion of the search value.
92. The method of claim 91 wherein selecting the portion of the search value comprises selecting the portion of the search value in accordance with a configuration value within the integrated circuit device.
93. The method of claim 91 wherein generating an index based on the search value comprises:
- assembling dispersed fields of bits within the search value to form a search key, and generating the index based on the search key.
94. The method of claim 93 further comprising masking selected bits within the search key prior to generating the index.
95. The method of claim 94 wherein masking selected bits within the search key comprises masking bits within the search key in accordance with a configuration value within the integrated circuit device.
96. A method of operation within an integrated circuit device, the method comprising:
- generating a plurality of priority values in response to a first instruction, each priority value indicating a storage capacity of a respective one of a plurality of circuit blocks; and
- generating, based on the priority values, a block identifier that identifies one of the circuit blocks.
97. The method of claim 96 wherein generating the block identifier based on the priority values comprises generating a block identifier that identifies a least filled one of the plurality of circuit blocks.
98. The method of claim 96 wherein generating the block identifier based on the priority values comprises generating a block identifier that identifies a most filled one of the plurality of circuit blocks.
99. The method of claim 96 further comprising storing in response to generation of the block identifier, a data value in the one of the plurality of circuit blocks identified by the block identifier.
100. A method of operation within an integrated circuit device, the method comprising:
- generating a plurality of indices based on a search value; and
- for each of a plurality of circuit blocks within the integrated circuit device; selecting one of the indices; retrieving a data value from a first storage location within the circuit block, the first storage location being indicated by the one of the indices; and determining whether the date value matches the search value.
101. The method of claim 100 wherein generating the plurality of indices based on the search value comprises generating a plurality of indices that each have fewer constituent bits than the search value.
102. The method of claim 100 wherein generating the plurality of indices based on the search value comprises generating each of the plurality of indices based on a selected portion of the search value.
103. The method of claim 100 wherein selecting one of the indices comprises selecting one of the indices in accordance with a configuration value within the integrated circuit.
104. The method of claim 100 wherein determining whether the data value matches the search value comprises comparing a selected portion of the data value with a selected portion of the mask value.
4152762 | May 1, 1979 | Bird et al. |
4813002 | March 14, 1989 | Joyce et al. |
4958377 | September 18, 1990 | Takahashi |
5129074 | July 7, 1992 | Kikuchi et al. |
5359720 | October 25, 1994 | Tamura et al. |
5386413 | January 31, 1995 | McAuley et al. |
5414704 | May 9, 1995 | Spinney |
5440715 | August 8, 1995 | Wyland |
5485418 | January 16, 1996 | Hiraki et al. |
5515370 | May 7, 1996 | Rau |
5526504 | June 11, 1996 | Hsu et al. |
5530958 | June 25, 1996 | Agarwal et al. |
5574871 | November 12, 1996 | Hoyt et al. |
5642322 | June 24, 1997 | Yoneda |
5706492 | January 6, 1998 | Hoyt et al. |
5724538 | March 3, 1998 | Morris et al. |
5818786 | October 6, 1998 | Yoneda |
5870324 | February 9, 1999 | Helwig et al. |
5903751 | May 11, 1999 | Hoyt et al. |
5920886 | July 6, 1999 | Feldmeier |
5944817 | August 31, 1999 | Hoyt et al. |
5999435 | December 7, 1999 | Henderson et al. |
6006306 | December 21, 1999 | Haywood et al. |
6011795 | January 4, 2000 | Varghese et al. |
6098147 | August 1, 2000 | Mizuhara |
6161144 | December 12, 2000 | Michels et al. |
6199140 | March 6, 2001 | Srinivasan et al. |
6226710 | May 1, 2001 | Melchior |
6289414 | September 11, 2001 | Feldmeier et al. |
6362992 | March 26, 2002 | Cheng |
6370613 | April 9, 2002 | Diede et al. |
6374349 | April 16, 2002 | McFarling |
6389506 | May 14, 2002 | Ross et al. |
6393544 | May 21, 2002 | Bryg et al. |
6499081 | December 24, 2002 | Nataraj et al. |
6735670 | May 11, 2004 | Bronstein et al. |
20030093616 | May 15, 2003 | Slavin |
- J. Da Silva and I. Watson, “Pseudo-Associative Store with Hardware Hashing,” IEE Proceedings, Computers and Digital Techniques, vol. 130, Pt. E, No. 1, Jan. 1, 1983, pp. 19-24.
- D. Knuth, “The Art of Computer Programming, vol. 3, Sorting and Searching, Second Edition,” Addison Wesley Longman, 1998, pp. 541-545.
- V. Srinivasan, S. Suri and G. Varghese, “Packet Classification using Tuple Space Search,” Proceedings of SIGCOMM, 1999, pp. 135-146.
- Z. Cao, Z. Wang and E. Zegura, “Performance of Hashing-Based Schemes for Internet Load Balancing,” Proc. IEEE INFOCOM 2000, Conf. on Computer Comm., vol. 1, 19th Annual Joint Conf. of the IEEE Computer and Comm. Soc., Tel Aviv, Israel, Mar. 26-30, 2000, pp. 1-10.
- A. Broder and M. Mitzenmacher, “Using Multiple Hash Functions to Improve IP Lookups,” Proceedings of IEEE INFOCOM, 2001, pp. 1454-1463.
- Motomura, M., et al., “A 1.2 Million Transistor, 33 MHz, 20-b Dictionary Search Processor (DISP) ULSI with a 160-kb CAM,” IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1158-1165.
- Robinson, I., “Patern-Addressable Memory,” IEEE Micro, vol. 12, No. 3, Jun. 1992, pp. 20-30.
- Shah, D. and Gupta, P., “Fast Incremental Updates on Ternary-CAMs for Routing Lookups and Packet Classification,” IEEE Micro, 21(1), Jan. 2001, pp. 1-9.
- Waldvogel et al., “Scalable High-Speed Prefix Matching,” ACM Transactions on Computer Systems, vol. 19, No. 4 Nov. 2001, pp. 440-482.
- Kobayashi, M. and Murase, T., “A Processor Based High-Speed Longest Prefix Match Search Engine,” IEEE 2001, pp. 233-239.
- Huang et al., “A Fast IP Routing Lookup Scheme for Gigabit Switching Routers,” IEEE 1999, pp. 1429-1436.
- Huang, Nen-Fu and Zhao, Shi-Ming, “A Novel IP-Routing Lookup Scheme and Hardware Architecture for Multigigabit Switching Routers,” IEEE Journal on Selected Areas in Communications, vol. 17, No. 6, Jun. 1999, pp. 1093-1104.
- V. Srinivasan and G. Varghese, “Fast Address Lookups Using Controlled Prefix Expansion,” ACM Transactions on Computer systems, vol. 17, No. 1, Feb. 1999, pp. 1-40.
- Gupta et al., “Routing Lookups in Hardware at Memory Access Speeds,” Proc. Infocom, San Francisco, CA, Apr. 1998, pp. 1-8.
- Waldvogel et al., “Scalable High Speed IP Routing Lookups,” SIGCOMM, Cannes, France, 1997, pp. 25-35.
Type: Grant
Filed: Feb 1, 2002
Date of Patent: Aug 23, 2005
Assignee: NetLogic Microsystems, Inc. (Mountain View, CA)
Inventors: Jose P. Pereira (Cupertino, CA), Sunder R. Rathnavelu (Marlboro, NJ), Rodolfo G. Beraha (Redwood City, CA), Lewis M. Carroll (Plano, TX), Ronald S. Jankov (Woodside, CA)
Primary Examiner: Kevin Verbrugge
Attorney: Shemwell Gregory & Courtney LLP
Application Number: 10/061,941