Abstract: A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Abstract: The application discloses an analog content addressable memory (CAM) device, an analog CAM cell and a method for data searching and comparing thereof. The CAM cell includes: a first memory cell and a second memory cell coupled to each other, wherein the analog CAM cell stores analog storage data which is corresponding to a match range, the match range is determined based on first and second threshold voltages of the analog CAM cell; an analog search data is converted into first and second analog search voltages; the first and the second memory cells receive the first and the second analog search voltages; and the analog CAM memory cell generates a memory cell current, or the analog CAM memory cell keeps or discharges a match line voltage on a match line coupled to the analog CAM memory cell.

Abstract: A logical array having a plurality of memory banks is constructed, wherein each of the plurality of memory banks is split into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The location of a data component stored in the memory component is determined by locating elements stored in a particular slot of the plurality of slots; and performing a corrective search on the located elements in the particular slot to locate a particular element. The data component is accessed based on the location of the particular element.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.

Abstract: A network element includes one or more ports and a packet processor. The one or more ports are to transmit and receive packets over a network. The packet processor is to apply a plurality of rules to the packets, each rule specifying (i) expected values for each header field of a group of header fields of the packets, including, for a given header field in the group, at least a set of multiple expected values, (ii) a group ID associated with the set, and (iii) an action to be applied to the packets whose header fields match the expected values.

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

Abstract: A content addressable memory circuit comprising: a memory device array including multiple memory devices coupled for simultaneous access to memory address locations that share a common memory address; multiple virtual modules (VMs), wherein each VM stores a data set that includes key values stored within an assigned memory address range within the memory array that are assigned to the VM; wherein each VM, stores a virtual hash table in non-transitory memory, that associates hash values with memory addresses within an assigned memory address range of the VM; hash logic is operable to determine a hash value, based upon a received key value and a respective assigned memory address range; and memory controller logic is operable to use a virtual hash table to access a memory address in an assigned memory address range, based upon the determined hash value.

Abstract: A method for translating memory addresses in a manycore system is provided, which is executed by one or more processors, and includes receiving identification information of a thread accessing a memory associated with one or more cores of a cluster that includes a plurality of cores, receiving a virtual address of data accessed by the thread, and determining a physical address of data in the memory based on the virtual address and the identification information of the thread.

Abstract: One embodiment is a first computing system configured to control a second computing system, a software module configured to attempt to interact with the second computing system once the second computing system is brought to a first state by the first computing system, and an admittance mechanism configured to determine if the interaction is allowed to occur.

Abstract: Novel tools and techniques are provided for implementing data packet processing, data packet capture, data packet storage, data packet retrieval, and data packet distribution. In various embodiments, a method might include detecting, with a computer, network traffic comprising one or more data packets within a network. Based on a detection of the network traffic comprising the one or more data packets within the network, the method might include capturing the one or more data packets to move the one or more data packets from the network to a storage of the computer. Next, the method might include determining one or more attributes associated with each captured data packet. Based on a determination of the one or more attributes, the method might additionally include storing each captured data packet according to the one or more first attributes in the storage of the computer.

Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.

Abstract: Apparatus and methods of artificial intelligent based provision of digital content where and when the digital content is needed based upon where an agent is located and a purpose for accessing the content. A location of a user seeking to access the digital content may be used that enables access to the content. Persistent digital content is linked to location coordinates. A physical onsite location may be linked with digital content to enable provision of a user interface with augmented reality that combines aspects of the physical area with location specific digital content. In addition, access to digital content may be limited to users in defined access areas.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Abstract: Techniques for improved searching and querying in computer-based reasoning systems are discussed and include receiving multiple new multidimensional data element to store in a computer-based reasoning data model; determining a feature bucket for each feature of each data element and storing a reference identifier in the feature bucket(s). A query on the computer-based reasoning system includes input data element (e.g., an actual data element, or a set of restrictions on features). For each feature in the input data element, feature buckets are determined, candidate results are determined based on whether cases have related feature buckets, and the results are determined based at least in part on the candidate results. In some embodiments, control of controllable systems may be caused based on the results.

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block comprising a plurality of key tables each storing a respective plurality of stored search keys. The memory system further includes a processing device that receives, from a requestor, an input search key and an indication of one of the plurality of key tables and identifies a match between the input search key and one of the plurality of stored search keys in the one of the plurality of key tables. The one of the plurality of stored search keys has an associated offset value indicating a location in a sorted string table (SSTable) corresponding to the one of the plurality of key tables. The processing device further reads the offset value from the one of the plurality of key tables and returns, to the requestor, the offset value read from the one of the plurality of key tables. The requestor can retrieve, from the location in the SSTable, data representing a value associated with the input search key.

Abstract: A ternary content addressable memory is provided comprising; a memory device that includes a plurality of memory address locations; hash logic operative to determine a hash value, based upon a ternary key, wherein the determined hash value corresponds to a memory address location of the memory device; an encoder operable to convert the ternary key to a binary bit representation; wherein converting includes determining binary mapping bits based upon number and positions of ternary non-X (don't care) value bits of the ternary key; wherein converting further includes determining a different binary data bit to correspond to each different ternary non-X value bit of the ternary key; and memory controller logic to cause the memory device to store the binary bit representation at the memory address location that corresponds to the determined hash value.

Abstract: An algorithmic TCAM based ternary lookup method is provided. The method stores entries for ternary lookup into several sub-tables. All entries in each sub-table have a sub-table key that includes the same common portion of the entry. No two sub-tables are associated with the same sub-table key. The method stores the keys in a sub-table keys table in TCAM. Each key has a different priority. The method stores the entries for each sub-table in random access memory. Each entry in a sub-table has a different priority. The method receives a search request to perform a ternary lookup for an input data item. A ternary lookup into the ternary sub-table key table stored in TCAM is performed to retrieve a sub-table index. The method performs a ternary lookup across the entries of the sub-table associated with the retrieved index to identify the highest priority matched entry for the input data item.

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.

Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.

Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.

Abstract: Present disclosure relates to a method and a system for searching through a Ternary Content Addressable Memory (TCAM). The system comprises a Digital Light Processing System (DLP) receiving an input query. The DLP comprises a 2-Dimensional array of digital micro mirrors configured for reflecting light from one or more input sources in the TCAM to a predefined position. The system further comprises a detection screen having a detection area. The detection area is configured for generating an image of a resultant pixel according to the reflection of the light, wherein the resultant pixel corresponds to a search result for an input query.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: Secure communication between users and resources of an electrical infrastructure and associated systems and methods. A representative secure distributed energy resource (DER) communication system provides for the creation of trust rules that govern the permitted communications between users and resources of an electrical infrastructure system, and the enforcement of the trust rules.

Abstract: In order to control a technical system using a control model, a transformation function is provided for reducing and/or obfuscating operating data of the technical system so as to obtain transformed operating data. In addition, the control model is generated by a model generator according to a first set of operating data of the technical system. In an access domain separated from the control model, a second set of operating data of the technical system is recorded and transformed by the transformation function into a transformed second set of operating data which is received by a model execution system. The control model is then executed by the model execution system, by supplying the transformed second set of operating data in an access domain separated from the second set of operating data, control data being derived from the transformed second set of operating data.

Abstract: Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.

Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.

Abstract: A method includes automatically determining a component of a security label for each first record in a first table of a database having multiple tables, including: identifying a second record related to the first record according to a foreign key relationship; identifying a component of the security label for the second record; and assigning a value for the component of the security label for the first record based on the identified component of the security label for the second record. The method includes storing the determined security label in the record.

Abstract: A storage system and method for automatic data phasing are disclosed. In one embodiment, a storage system is configured to receive, from a host, data to be written in the memory and an indication of an expected lifespan of the data; and determine whether to perform a garbage collection operation on the data based on the expected lifespan of the data. Other embodiments are provided.

Abstract: A method of translating a virtual address into a physical memory address in an ARM System Memory Management Unit version 3 (SMMUv3) system includes searching a Configuration Cache memory for a matching tag that matches an associated tag upon receiving the virtual address and the associated tag, and extracting, in a single memory lookup cycle, a matching data field associated with the matching tag when the matching tag is found in the Configuration Cache memory. A matching data field of the Configuration Cache memory includes a matching Stream Table Entry (STE) and a matching Context Descriptor (CD), both associated with the matching tag. The Configuration Cache memory may be configured as a content-addressable memory. The method further includes storing entries associated with a multiple memory lookup cycle virtual address-to-physical address translation into the Configuration Cache memory, each of the entries including a tag, an associated STE and an associated CD.

Abstract: This disclosure generally relates to data delivery in distributed applications. One example method includes identifying a data source associated with a shuffle operation, the data source configured provide data from a data set associated with the shuffle operation; identifying a data sink associated with the shuffle operation, the data sink configured to receive data provided by the data source; associating a shuffler component with the shuffle operation, the shuffler component configured to receive data from the data source and provide the data to the data sink; receiving, by the shuffler component, a first data portion from the data source; providing, by the shuffler component, the first data portion to the data sink; receiving, by the shuffler component, a second data portion from the data source, the second data portion being received from the data source prior to or concurrent with providing the first data portion to the data sink.

Abstract: A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.

Abstract: For each of multiple storage volumes of a distributed storage system, it is determined whether the storage volume has a relatively high potential deduplicability or a relatively low potential deduplicability. Responsive to determining that the storage volume has the relatively high potential deduplicability, a first write flow is executed for each of a plurality of write requests directed to the storage volume, the first write flow utilizing content-based signatures of respective data pages of the storage volume to store the data pages in storage devices of the distributed storage system. Responsive to determining that the storage volume has the relatively low potential deduplicability, a second write flow is executed for each of a plurality of write requests directed to the storage volume, the second write flow utilizing non-content-based signatures of respective data pages of the storage volume to store the data pages in storage devices of the distributed storage system.

Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

Abstract: In a network device, a hash calculator generates a lookup hash value from data fields associated with a packet received by the network device. A compressed lookup key generator generates a compressed lookup key for the packet using the lookup hash value. A content addressable memory (CAM) stores compressed patterns corresponding to compressed lookup keys, uses the compressed lookup key received from the compressed lookup key generator to determine if the received compressed lookup key matches any stored compressed patterns, and outputs an index corresponding to a stored compressed pattern that matches the compressed lookup key. A memory stores uncompressed patterns corresponding to the compressed patterns stored in the CAM, and retrieves an uncompressed pattern using the index output by the CAM. A comparator generate a signal that indicates whether the uncompressed pattern retrieved from the memory matches the data fields associated with the packet.

Abstract: A collection of rules comprising fields that may have wildcard values. The method includes defining first and second subsets of the fields, the second subset being exclusive of the first subset. Intersections of overlapping fields of the first subset are added to the first subset to form an augmented first subset. Metadata from the augmented first subset and the fields not selected for the first subset are combined to define second parts of the rules. Data items are classified by matching a search key to one of the first parts and one of the second parts of the rules.

Abstract: A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Abstract: A framework for memory optimization of database indexes, and in particular for aging full-text index data, is described herein. In one embodiment, if, while a database table is aged, there are index tables associated with the database table, the associated index tables are automatically aged. This way, the system memory footprint will be reduced, leading to reduced cost as less system memory is required to perform remaining operations, and leading to increased performance as more system memory is available for other operations.

Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.

Abstract: Methods, systems, and computer-readable mediums for managing forwarding equivalence class (FEC) hierarchies, including obtaining a forwarding equivalence class (FEC) hierarchy; making a first determination that a first hardware component supports a maximum levels of indirection (MLI) quantity; making a second determination that the FEC hierarchy has a hierarchy height; based on the first determination and the second determination, performing a comparison between the MLI quantity and the hierarchy height to obtain a comparison result; and based on the comparison result, performing a FEC hierarchy action set.

Abstract: A processing device monitors performance of a first thread of a first application executing on one of a plurality of processing cores of a storage system. The first thread comprises an internal scheduler controlling switching between a plurality of sub-threads of the first thread, and an external scheduler controlling release of the processing core by the first thread for use by at least a second thread of a second application different than the first application. In conjunction with monitoring the performance of the first thread in executing the first application, the processing device maintains a cumulative suspend time of the first thread over multiple suspensions of the first thread, with one or more of the multiple suspensions allowing at least the second thread of the second application to execute on the processing core, and generates performance measurements for sub-threads of the first thread using the cumulative suspend time.

Abstract: Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or system calls in the host program corresponding to the different functions then use jump logic to pass function selection values to an accelerator program in the accelerator that inform the accelerator program which function it is being instructed to perform. This jump logic can be generated by an accelerator compiler and then inserted into the host program as a host compiler generates the executable (e.g., the compiled binary) for the host program.

Abstract: Methods, apparatus, and processor-readable storage media for management of unit-based virtual accelerator resources are provided herein. An example computer-implemented method includes obtaining multiple accelerator device resource consumption measurements, wherein the measurements represent multiple accelerator device resource types consumed by one or more accelerator devices over a defined temporal interval; computing a composite unit of measurement of accelerator device resource consumption, attributable to the one or more accelerator devices over the defined temporal interval, by normalizing the multiple accelerator device resource consumption measurements using a scaling factor that is based at least in part on one or more static aspects of the one or more accelerator devices; and outputting the composite unit of measurement to at least one user.

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Abstract: A method is provided for error detection in a ternary content addressable memory, TCAM, preferably in real-time, wherein the error detection is initiated with a read operation at a specified input address (200), wherein an additional random access memory, RAM, is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries (210) which each consist of data and a mask are placed at the same address locations. In addition, a method is provided for error detection in a TCAM, preferably in real-time, wherein the error detection is triggered by the found of searched input key (400) and starts with a read operation at a specified memory address (410), wherein an additional RAM is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries (420) which each consist of data and a mask are placed at the same address locations.

Abstract: A method includes: executing a first process includes receiving an entry that includes a kay and a value, selecting a first list from among a plurality of lists in accordance with a first hash value, adding, to the selected first list, a first identifier in association with the received entry, and storing the received entry in any of a first memory device and a second memory device that is greater in latency than the first memory device; and executing a second process that includes receiving a searching request for a value, selecting the first list based on the first hash value derived from the searching key in the received searching request, obtaining the first identifier from the first list selected in the second process, obtaining the entry associated with the first identifier obtained in the second process, and outputting the value in the entry obtained in the second process.

Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.