Single-step processing and selecting debugging modes
In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.
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This invention relates to programmable processors.
A programmable processor, such as a microprocessor for a computer or a digital signal processing system, may execute instructions far more rapidly than a human being can execute them. Consequently, when a processor makes an error, which may occur for several reasons, the error usually occurs so quickly that a human cannot directly observe what led to the error. Various techniques, generally called “debugging,” may be employed to track down the source or sources of the error.
Control unit 12 may control the flow of instructions and data through pipeline 14. For example, during the processing of an instruction, control unit 12 may direct the various components of pipeline 14 to decode the instruction and perform the corresponding operation including, for example, writing the results back to main memory 16.
Control unit 12 may include exception handler 20, which may hold addresses of pre-defined instructions to be processed in pipeline 14 when an exception is raised. Control unit 12 may also include control register 25, which stores data related to control functions. Control bits 23A and 23B in control register 25 comprise information related to single-step debugging techniques, as will be described in more detail below. The state of control bits 23A and 23B can be sensed by pipeline 14 via two-bit bus 24.
Main memory 16 may store information such as instructions and data. Main memory 16 may comprise static random access memory (SPAM), dynamic random access memory (DRAM), flash memory or the like. Processor 10 may include components not shown in
Pipeline 14 typically includes stage registers 42 that are used as temporary memory storage elements and may be used to pass results and other information from stage to stage. In addition to registers 42 and data registers 40, pipeline 14 may include additional memory elements or registers for holding instructions, addresses, data or other information.
Pipeline 14 ordinarily processes instructions in a substantially concurrent manner, with several instructions in pipeline 14 in different stages. For example, while one instruction is in the WB stage, another instruction may be in the EX stage, and a further instruction may be in the AC stage. In some circumstances, however, it may be advantageous to process one instruction, then examine the states of processor 10 and/or the contents of the various registers before completing the processing of the following instruction. Processing instructions in this fashion is called “single-step debugging” and may be desirable, for example, during debugging. Debugging may involve, for example, executing an instruction and examining the contents of memory elements such as registers before executing the next instruction. Single-step debugging and examination of memory elements may allow a user to understand whether an error is hardware-based or software-based, to identify problems in the hardware or software, and to observe the interaction among software instructions. Debugging may take place during development of processor 10, before processor 10 is incorporated into a product. Debugging and may also be performed after processor 10 is incorporated into a product.
When a user wants to begin single-step debugging, the user may give a command to processor 10 by way of an input-output device 22, such as a keypad. Processor 10 may support different modes of single-step debugging, and the user may further specify the desired manner.
One mode of single-step debugging, illustrated in
In response to the single-step exception, control unit 12 typically cancels instructions in the pipeline 14 (56) and routes control to exception handler 20 (58). Exception handler 20 includes addresses of pre-defined instructions to be processed in pipeline 14 when a single-step exception is raised (60). Such instructions may include sensing the processor states and outputting information about the states via input/output interface 18 (62), sensing the register contents and outputting the contents (64), and clearing the exception (66). The instructions may be adapted to sense particular register contents or particular processor states. In addition, outputting information may include sending information to input/output device 22, such as a printer or display screen, and may also include writing the information to main memory 16. The instructions (60) shown in
When the exception is cleared (66) and other instructions of the exception handler have been executed, control unit 12 may continue the single-step debug process (68) by sending another instruction through pipeline 14 (52), which results in another exception upon completion (54). The instruction to be sent is typically one that was previously sent through pipeline 14 but was cancelled (56) before execution was completed, due to the previously handled exception. The user may also choose to terminate single-step operation (70).
Single-step debugging by taking single-step exceptions may be useful for some purposes, and is usually fast and inexpensive, and usually requires no additional hardware. This technique may not be suitable for all purposes, however. For example, this technique may not be effective for debugging the exception handler itself. In addition, the technique may not be effective for debugging protected system resources such as high-level event-handling routines. High-level event-handling routines may have, for example, higher priorities than the exceptions, and consequently may take precedence over the exceptions and may prevent the exceptions from being raised.
Another approach to single-step debugging is to enter a high-level operating mode, such as emulation mode, and feed each instruction individually to pipeline 14. Generally speaking, a processor may have many modes of operation, such as a user mode and a supervisory mode, which will be discussed in more detail below. Emulation mode is a mode of operation adapted for operations such as debugging. Typically, in emulation mode pipeline 14 fetches instructions from an emulation instruction register, rather than from main memory 16 or an instruction cache. Pipeline 14 also typically reads and writes data from an emulation data register rather than from main memory 16 or a data cache.
To begin single-step debugging (80), an instruction is sent through pipeline 14 (82). When the instruction reaches the WB stage, pipeline 14 raises an emulation event (84). Emulation mode may be invoked in different ways for different processor architectures, such as by applying a signal to a particular processor port or by executing software designed to invoke emulator mode. Once in emulation mode, high-level processor functions and resources are available, and inputs and outputs to processor 10 are regulated. Control unit 12 typically cancels instructions in the pipeline 14 (86) and routes control to an emulation service routine (88). The emulation service routine includes instructions that may include sensing the processor states and outputting information about the states via input/output interface 18 (92) and sensing the register contents and outputting the contents (94). Outputting information may include sending information to an output register or to input/output device 22, and may include writing the information to main memory 16. Emulation mode generally is terminated by a “return” instruction, which returns processor 10 to the state in which it was operating before invoking emulation mode and includes the address of the next instruction to be fetched (96). Typically, return from emulation mode after each step (96) is automatic, so continued single-step debugging (98) may involve each single-step operation being separately commanded. If no command to enter emulation mode is given, the single-step operation terminates (100).
Control of single-step debugging can be regulated in many ways. An exemplary method to control single-step debugging, illustrated by
A number of embodiments of the invention have been described. For example, methods of single-step debugging have been described, by taking an exception after each instruction or by placing the processor in an emulation mode. The processor may be implemented in a variety of systems including general purpose computing systems, digital processing systems, laptop computers, personal digital assistants (PDA's) and cellular phones. In this context, the single-step debugging techniques discussed above may be readily used to test the system before or after a customer sale. In such a system, the processor may be coupled to a memory device, such as a FLASH memory device or a SRAM device, that stores an operating system and other software applications. These and other embodiments are within the scope of the following claims.
Claims
1. A computer implemented method comprising:
- assigning a state to a plurality of control bits, wherein the state is a first state when a first debugging mode is to be selected by the invocation of a first debug handler, and wherein the state is a second state when a second debugging mode is to be selected by the invocation of a second debug handler, and wherein the state is a third state when one of a plurality of debugging modes is to be selected as a function of a current operating mode of a processor; and
- invoking one of a plurality of debug handlers based on the state of the control bits, wherein the plurality of debug handlers includes the first debug handler and the second debug handler, and wherein the first debug handler comprises an emulation service routine and wherein the second debug handler comprises an exception handler.
2. The method of claim 1 wherein selecting the debugging mode as a function of the current operating mode of the processor comprises selecting a first debugging mode when the operating mode comprises a supervisor mode, and selecting a second debugging mode when the operating mode comprises a user mode.
3. The method of claim 1, wherein the first debug handler is capable of debugging the second debug handler.
4. The method of claim 1, further comprising using the first debug handler to debug the second debug handler.
5. The method of claim 1, further comprising determining whether to bypass said selecting one of a plurality of debugging modes as a function of a current operating mode of the processor and to instead select one of a plurality of debug modes without regard to the current operating mode of the processor.
6. A method comprising:
- receiving an instruction;
- receiving a signal;
- selecting a mode of debugging as a function of the signal, wherein selecting the debugging made comprises selecting a first debugging mode using a first debug handler when the signal is a first signal, selecting a second debugging mode using a second debug handler when the signal is a second signal, and selecting the debugging mode as a function of a current operating mode of a processor when the signal is a third signal;
- invoking one of plurality of debug handlers, wherein the plurality of debug handlers includes the first debug handler and the second debug handler; and
- executing the instruction.
7. The method of claim 6 further comprising raising an exception.
8. The method of claim 6 further comprising invoking an emulation event.
- 9.The method of claim 6 further comprising:
- sensing register contents; and
- outputting register contents.
10. The method of claim 6, wherein the instruction is received by the processor, and wherein the processor is adapted to operate in a plurality of states, the method further comprising:
- sensing states of the processor; and
- outputting states of the processor.
11. The method of claim 6, wherein:
- the first debugging mode comprises invoking an emulation event;
- the second debugging mode comprises raising an exception; and
- the selecting the debugging mode as a function of a current operating mode of a processor comprises selecting the first debugging mode when a current operating mode of the processor comprises a supervisor mode and selecting the second debugging mode when a current operating mode of the processor comprises a user mode.
12. The method of claim 6, wherein the selected debug mode comprises raising an exception after executing an instruction, and wherein the current operating mode of the processor comprises a supervisor mode.
13. A device comprising:
- a processor, the processor adapted to operate in a plurality of operating modes including an emulation mode;
- a control register adapted to store the state of at least one control bit; and
- a plurality of debug handlers, wherein the plurality of debug handlers includes a first debug handler and a second debug handler, and wherein the first debug handler comprises an emulation service routine and the second debug handler comprises an exception handler; wherein the processor is adapted to assign the state of the at least one control bit, wherein the state is a first state when a first debugging mode is to be selected by the invocation of a first debug handler, and wherein the state is second state when a second debugging mode is to be selected by the invocation of a second debug handler, and wherein the state is a third state when one of a plurality of debugging modes is to be selected as a function of a current operating mode of a processor.
14. The device of claim 13, wherein the processor is adapted to select one of a plurality of debugging modes as a function of the current operating mode of the processor.
15. The device of claim 13, wherein the processor is further adapted to select the first debugging mode when the current operating mode comprises a supervisor mode and to select the second debugging mode when the current operating mode comprises a user mode.
16. The device of claim 15, wherein the first debugging mode comprises an emulation debugging mode and wherein the second debugging mode comprises an exception debugging mode.
17. The device of claim 13, further comprising exception logic adapted to sense the state of the at least one control bit and to trigger an exception event as a function of the state of the at least one control bit.
18. The device of claim 13, further comprising emulation logic adapted to sense the state of the at least one control bit and to trigger an emulation event as a function of the state of the at least one control bit.
19. The device of claim 13, wherein the at least one control bit is a first control bit, the device further comprising a second control register adapted to store the state of a second control bit, and wherein the mode of single-step debugging is a function of the state of the second control bit.
20. The device of claim 13, wherein the processor is a digital signal processor.
21. A device comprising:
- a processor, the processor adapted to operate in a plurality of operating modes; and
- a register adapted to store the state of a signal;
- wherein the processor is adapted to select a debugging mode as a function of the signal, wherein selecting the debugging mode comprises selecting a first debugging mode using a first debug handler when the signal is first signal, selecting a second debugging mode using s second debug handler when the signal is a second signal, and selecting the debugging mode as a function of a current operating mode of the processor when the signal is a third signal; and
- wherein the processor is further adapted to invoke one of a plurality of debug handlers, wherein the plurality of debug handlers includes the first debug handler and the second debug handler.
22. The device of claim 21 further comprising a control register adapted to store the state of a control bit, wherein the processor is adapted to select one of the plurality of debugging modes as a function of the state of the control bit.
23. The device of claim 22, further comprising
- an exception handler; and
- logic adapted to sense the state of the control bit and to trigger an exception event as a function of the state of the control bit.
24. The device of claim 22, further comprising logic adapted to sense the state of the control bit and to trigger an emulation event as a function of the state of the control bit.
25. The device of claim 21, wherein the processor is a digital signal processor.
26. The device of claim 21, wherein:
- the first debugging mode comprises invoking an emulation event;
- the second debugging mode comprises raising an exception; and
- said selecting the debugging mode as a function of a current operating mode of a processor comprises selecting the first debugging mode when a current operating mode of the processor comprises a supervisor mode and selecting the second debugging mode when a current operating mode of the processor comprises a user mode.
27. A method comprising:
- receiving an instruction;
- receiving a signal; and
- selecting a debugging mode, wherein said selecting a debugging mode comprises: selecting an emulation debugging mode when the signal is a first signal; selecting an exception debugging mode when the signal is a second signal; selecting the emulation debugging mode when the signal is a third signal and when a current operating mode of a processor comprises a supervisor mode; and selecting the exception debugging mode when the signal is the third signal and when the current operating mode of the processor comprises a user mode.
28. The method of claim 27, wherein the selected debugging mode comprises an exception debugging mode and wherein the current operating mode of the processor comprises a supervisor mode.
29. The method of claim 27, wherein the third signal signifies that the selected debugging mode should be one level higher than the current operating mode of the processor.
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Type: Grant
Filed: Dec 15, 2000
Date of Patent: Jan 10, 2006
Patent Publication Number: 20040073780
Assignees: Intel Corporation (Santa Clara, CA), Analog Devices, Inc. (Norwood, MA)
Inventors: Charles P. Roth (Austin, TX), Ravi P. Singh (Austin, TX), Tien Dingh (Cedar Park, TX), Ravi Kolagotla (Austin, TX), Marc Hoffman (Mansfield, MA), Russell Rivin (Holliston, MA)
Primary Examiner: Eddie Chan
Assistant Examiner: Charles Harkness
Attorney: Fish & Richardson P.C.
Application Number: 09/738,649
International Classification: G06F 9/00 (20060101);