Zero threshold voltage pFET and method of making same
A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
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This application is a divisional of U.S. application Ser. No. 10/250,190 filed Jun. 11, 2003 now U.S. Pat. No. 6,825,530, and incorporated by reference herein.
FIELD OF THE INVENTIONThe present invention relates generally to the field of semiconductors. More particularly, the present invention is directed to a zero threshold voltage pFET and a method of making the same.
BACKGROUND OF THE INVENTIONZero, or low, threshold voltage (ZVt) devices are useful in various types of integrated circuits (ICs). For example, ZVt field-effect transistors (FETs) are desirable in certain applications because of their high switching speed and low saturation voltage. ZVt FETs are useful in analog circuits, e.g., amplifiers and power supplies, and in digital circuits, e.g., for power supply decoupling in logic circuits, among other uses.
In the manufacture of semiconductor ICs, processing often begins with a p-doped wafer. Due to this p-doping, it is a relatively simple matter to form ZVt nFETs without the need to provide any masks in addition to the masks used to form the implanted wells of standard threshold voltage (Std-Vt) FETs. Since there are no additional costs needed for additional masks with respect to ZVt nFETs, Zvt nFETs may be called “free” devices. However, using conventional processing techniques, ZVt pFETs are not free devices, since they would have to be made using an additional counterdoping mask that would not be needed to form the n-well of a Std-Vt pFET. This is illustrated in
As shown in
An integrated circuit comprising a device that includes a substrate made of a material. The substrate includes a surface, an implanted well having a first dopant type and a lower portion distal from the surface. A pocket consisting of the material is formed within the implanted well between the lower portion of the implanted well and the surface of the substrate. An insulator is located proximate the surface of the substrate above the pocket. An electrode is located proximate the insulator and is located substantially in registration with the pocket.
A method of forming an integrated circuit device on a substrate made of a material and having a surface. The method comprises the step of providing a mask to the substrate that protects a pocket of the substrate adjacent the surface of the substrate. An implanted well is formed so that the implanted well isolates the pocket. An insulator is formed proximate the surface of the substrate above the pocket. An electrode is formed proximate the insulator above the pocket.
For the purpose of illustrating the invention, the drawings show a form of the invention that is presently preferred. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:
IC 100 generally includes a substrate 112, such as a p-doped wafer or combination of one or more epitaxial layers and a wafer, that provides the basic structure of ZVt pFET 104 and Std-Vt nFET 108. ZVt pFET 104 includes an n-well 116, a source 120, a drain 124, a gate insulator 128, a gate 132, and a pocket 136 of p-substrate material located between the gate and the lower portion 140 of the n-well. The formation of pocket 136 is an important aspect of the present invention, since this may be accomplished without additional masks. Thus, ZVt pFET 104 may be considered a “free device,” as described in the background section above. Std-Vt nFET 108 may be a conventional nFET that includes a p-well 144, a source 148, a drain 152, a gate insulator 156, and a gate 160. STIs 164 may be provided around ZVt pFET 100 and Std-Vt nFET 108 as needed to isolate the regions of these devices from one another and other surrounding devices (not shown). STIs 164 may be formed using any of the well-known methods practiced in the art. As those skilled in the art will appreciate, STIs 164 may be formed before or after well implanting is performed.
Although not shown, wherever Std-Vt pFETs are desired, n-well mask 168 would include conventional n-well apertures. Generally, an aperture for forming ZVt pFET 104 is the same as a conventional n-well aperture, but with pocket-masking region 184, for creating pocket 136 (
As can be seen in
Depending upon the width W of pocket-masking region 184, the depth of n-well 116, and dopant concentration in the lower portion 140 of the n-well, among other variables, skewed implantation may be used to supplement annealing or to eliminate the need to anneal substrate. As is readily apparent, implanting dopant atoms at an angle skewed from normal may be used to implant these atoms farther underneath pocket-masking region 184 of n-well mask 168 than implantation performed normal to the surface of substrate 112 could achieve. If width W of pocket-masking region 184 is small enough and the angle of implantation is large enough with respect to a normal from the surface of substrate 112, implantation may be great enough that atoms implanted from one side of the pocket-masking region may extend into the region doped with atoms implanted from the opposite side of the pocket-masking region, particularly when implantation is performed at multiple angles in opposing directions. These skewed implantations are represented by arrows 188 in
After merged n-well 116 has been formed, substrate 112 may be further processed to form the remaining structures of ZVt pFET 104 and Std-Vt nFET 108. For example,
Although the invention has been described with respect to forming a ZVt pFET 104 on a p-doped substrate 112, those skilled in the art will readily appreciate that a ZVt nFET may similarly be formed on a n-doped substrate. In addition, those skilled in the art will understand that IC devices other than ZVt FETs, e.g., ZVt capacitors, may be made in accordance with the present invention. A ZVt capacitor is similar to a ZVt FET but would have a larger “gate” electrode and no source (or drain).
While the present invention has been described in connection with a preferred embodiment, it will be understood that it is not so limited. On the contrary, it is intended to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined above and in the claims appended hereto.
Claims
1. A method of forming an integrated circuit device on a substrate made of a material and having a surface, comprising the steps of:
- a) providing a mask to the substrate that protects a pocket of the substrate adjacent the surface of the substrate;
- b) forming an implanted well so that said implanted well isolates said pocket;
- c) forming an insulator proximate the surface of the substrate above said pocket; and
- d) forming an electrode proximate said insulator above said pocket.
2. A method according to claim 1, wherein said implanted well has a lower portion and step b includes forming a ring-shaped precursor well and annealing the substrate so that regions of said lower portion merge with one another so as to isolate said pocket.
3. A method according to claim 1, wherein step b includes implanting atoms at one or more angles skewed with respect to a normal from the surface of the substrate.
4. A method according to claim 1, wherein the integrated circuit device is a ZVt FET.
5. A method according to claim 4, wherein the ZVt FET is a pFET.
6. A method according to claim 1, wherein said electrode is a gate.
7. A method according to claim 6, further comprising the steps of forming a source and a drain in the substrate.
8. A method according to claim 1, wherein the substrate is a wafer.
9. A method according to claim 1, wherein the material is p-doped silicon and said implanted well is an n-well.
10. A method according to claim 1, wherein step b) is at least partially performed using said mask.
11. A method according to claim 1, wherein said pocket has a center and step d) comprises forming said electrode substantially over said center.
12. A method of forming an integrated circuit having a plurality of Std-Vt FETs and a plurality of ZVt FETs on a doped substrate, comprising the steps of:
- a) providing a mask to the doped substrate for protecting a plurality of first areas in which Std-Vt FETs are to be formed and for protecting a pocket within each of a plurality of second areas in which ZVt FETs are to be formed;
- b) forming an implanted well within the substrate at each area other than said first and second areas, said implanted well isolating a corresponding respective said pocket; and
- c) forming a gate insulator and a gate in each of said second areas above said corresponding respective pockets.
13. A method according to claim 12, wherein each of said implanted wells has a lower portion and step b includes forming a plurality of ring-shaped precursor wells and annealing the substrate so that regions of said lower portions merge with one another so as to isolate said pockets.
14. A method according to claim 12, wherein step b includes implanting atoms at one or more angles skewed with respect to a normal from a surface of the substrate.
15. A method according to claim 12, further comprising the steps of forming a source and a drain in each of said second areas.
16. A method according to claim 12, wherein step b) is at least partially performed using said mask.
17. A method according to claim 12, each said pocket includes a center and step c) includes forming said gate insulator and said gate substantially over said center.
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Type: Grant
Filed: May 14, 2004
Date of Patent: Feb 28, 2006
Patent Publication Number: 20040251475
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Jeffrey S. Brown (Middlesex, VT), Chung H. Lam (Williston, VT), Randy W. Mann (Poughquag, NY), Jeffery H. Oppold (Richmond, VT)
Primary Examiner: Mai-Huong Tran
Attorney: Downs Rachlin Martin PLLC
Application Number: 10/845,835
International Classification: H01L 21/336 (20060101);