Abstract: A photo-EMF detector including a shield to prevent a portion of the detector from illumination. The shield prevents the generation of unwanted noise-currents, thus increasing the performance of the photo-EMF detector.

Abstract: A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film.

Abstract: A semiconductor integrated circuit comprises a semiconductor substrate, a heat-producing circuit element formed in a multi-layer structure on the semiconductor substrate and performing a predetermined operation while producing heat of a relatively high temperature, a plurality of temperature-dependent circuit elements, each formed in a multi-layer structure in a predetermined location on the semiconductor substrate, performing a predetermined operation depending on temperature of the heat-producing circuit element, and each having a constant relationship in temperature-related properties with each another, and a heat conductive layer having a heat conductivity higher than a heat conductivity of the semiconductor substrate, and covering at least a heat-producing portion of the heat-producing circuit element and the plurality of temperature-dependent circuit elements continuously so as to conduct the heat produced by the heat-producing circuit element to the plurality of temperature-dependent circuit elements.

Abstract: A chip package has lead frame, chip, generic wires, at least one characterized wire, ground wires and insulation material. The lead frame includes die pad, generic leads and at least a characterized lead structure. Generic leads and the characterized lead structure are aligned at peripheral region of the die pad. The characterized lead structure has a cross-sectional area perpendicular to the direction where signals transmit, which is larger than each generic lead. The chip is on the die pad. The generic wires connect the chip to the generic leads. The characterized wire connects the chip to the characterized lead structure. The characterized wire is for transmitting an identical signal between the chip and the characterized lead structure. Ground wires connect the chip to the die pad, and are located at both sides of the characterized wires. The insulation material encapsulates lead frame, chip, generic wires, characterized wire and ground wires.

Abstract: Extremely thin chips laminated to a non-ultraviolet ray curing type adhesive tape are peeled from the tape without giving rise to cracks and chippings. In a center portion of a suction block used for peeling off a chip laminated to a dicing tape, three blocks which push the dicing tape upwardly are incorporated. With respect to these blocks, inside the first block having a largest diameter, there is a second block having a diameter smaller than the diameter of the first block. Further, inside the second block, there is a third block having the smallest diameter. To peel off a chip by pushing a back surface of the dicing tape with the blocks, first of all, the three blocks are simultaneously pushed upwardly by a certain amount and, thereafter, the intermediate block and the inner block are further pushed upward, and, finally, the inner block is further pushed upward.

Abstract: A multiple-bit memory cell for use in a magnetic random access memory circuit includes a first adiabatic switching storage element having a first anisotropy axis associated therewith and a second adiabatic switching storage element having a second anisotropy axis associated therewith. The first and second anisotropy axes are oriented at a substantially non-zero angle relative to at least one bit line and at least one word line corresponding to the memory cell. The memory cell is configured such that two quadrants of a write plane not used for writing one of the storage elements can be beneficially utilized to write the other storage element so that there is essentially no loss of write margin in the memory cell.

Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle ? is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

Abstract: A multi-chip package is provided. A first die pad has a first chip attaching surface and a first unoccupied surface. A second die pad has a second chip attaching surface and a second unoccupied surface. The connecting structures are used for connecting the first die pad and the second die pad. The inner leads has wire connecting surfaces. The wire connecting surfaces, the first chip attaching surface and the second unoccupied surface face the same direction. A first chip has a first active surface and a first inactive surface. The first inactive surface is attached to the first chip attaching surface. A second chip has a second active surface and a second inactive surface. Part of the second active surface is attached to the second chip attaching surface. The wires are used for electrically connecting the first active surface and the second active surface to the wire connecting surfaces.

Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.

Abstract: A modular light emitting diode (LED) mounting configuration is provided including a light source module having a plurality of pre-packaged LEDs arranged in a serial array. The module is connected to a heat dissipating plate configured to mount to an electrical junction box. Thus, heat from the LEDs is conducted to the heat dissipating plate and to the junction box. A sensor is configured to detect environmental parameters and a driver is configured to illuminate the LEDs in response to the environmental parameters, thereby selectively configuring the LEDs to function in a wide variety of useful applications.

Abstract: The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation region. These dopant ions are further surrounded by dopant ions of the first conductivity type with a second impurity concentration. The resulting isolation region structure increases the capacitance of the photodiode by allowing the photodiode to possess a greater charge collection region while suppressing the generation of dark current.

Abstract: An embedded IC packaging structure is disclosed. The embedded IC packaging structure allows a micro-electro-mechanical system (MEMS) having a great number of electrodes to be bonded to another semiconductor device, such as a driver IC, using a secondary substrate, thus ensuring an easy bonding process, providing IC devices capable of executing high-speed signal processing, reducing the production costs, and improving the production yield of the IC devices.

Abstract: Disclosed is a multi-layered PCB of mobile communication terminals that may improve ESD protection of LCD through efficiently protecting LCD signal lines such as data lines and control lines from ESD. According to the present invention, the efficient arrangement of GND regions around the LCD signal lines improve ESD features of sub-LCD and main-LCD and reduce defects by ESD, so that reliability of mobile communication terminals may be improved and the mobile communication terminals may stably operate against unexpected situation. Accordingly, it is possible to improve quality of mobile communication terminals and to reduce manufacturing cost due to efficient PCB arrangement.

Abstract: A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating layer; a charge storing layer disposed over the insulating layer; and another insulating layer disposed over the charge storing layer. A gate is disposed over the top insulting layer in the uppermost memory layer in the plurality of stacked memory layers.

Abstract: A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

Abstract: Magnetic tunnel junction (“MTJ”) element structures and methods for fabricating MTJ element structures are provided. An MTJ element structure may comprise a crystalline pinned layer, an amorphous fixed layer, and a coupling layer disposed between the crystalline pinned layer and the amorphous fixed layer. The amorphous fixed layer is antiferromagnetically coupled to the crystalline pinned layer. The MTJ element further comprises a free layer and a tunnel barrier layer disposed between the amorphous fixed layer and the free layer. Another MTJ element structure may comprise a pinned layer, a fixed layer and a non-magnetic coupling layer disposed therebetween. A tunnel barrier layer is disposed between the fixed layer and a free layer. An interface layer is disposed adjacent the tunnel barrier layer and a layer of amorphous material. The first interface layer comprises a material having a spin polarization that is higher than that of the amorphous material.

Abstract: A semiconductor device has a reduced number of external power terminals and is scaled down while suppressing power noise, and an electronic device is efficiently equipped with a bypass condenser. A package substrate has, on its surface, a semiconductor chip having a plurality of output circuits and at least one electrode for supplying a voltage to each of the output circuits, and is provided with external terminals on its back surface and has a plurality of wiring layers.

Abstract: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer.

Abstract: A ferroelectric memory device includes a first trench formed in a semiconductor substrate and having a first depth, a second trench formed in the substrate and having a second depth, a first element isolation insulating film buried in the first trench, a first gate electrode formed in a lower region of the second trench, a first insulating film formed in an upper region of the second trench, first and second diffusion layers formed in the substrate on both side surface in the second trench, a first ferroelectric capacitor disposed on the first diffusion layer, a first contact disposed on the first ferroelectric capacitor, a first wiring layer disposed on the first contact, a second contact disposed on the second diffusion layer, and a second wiring layer disposed on the second contact and disposed in the same level as that of the first wiring layer.

Abstract: A substrate having a built-in semiconductor apparatus includes: a semiconductor apparatus which comprises a first semiconductor chip having a first electrode pad formed on a main surface thereof, a protruding portion which is in contact with the first semiconductor chip and protrudes from a side surface of the first semiconductor chip to the outside, an apparatus wiring portion which is provided so as to extend from the first electrode pad onto a surface of the protruding portion, a conductive portion which is in connected with the apparatus wiring portion and provided on the apparatus wiring portion, and a sealing layer which covers the main surface and the surface of the protruding portion so as to expose a top face of the conductive portion; an insulating layer in which the semiconductor apparatus is embedded; an external terminal provided on the insulating layer; and a substrate wiring portion which electrically connects the conductive portion with the external terminal.