Ring oscillator for use in parallel sampling of high speed data
A ring oscillator has multiple stages that are independently adjustable. The delay is controlled using digital signals supplied to the stages. Each stage may receive two digital signals to control the delay with outputs of the particular stage controlling which of the two digital signals is used to control the delay through the stage at any particular time. The stages of the ring oscillator may be biased towards either supplying a faster or slower output signal. Each stage of the ring oscillator includes a tail node having a gate of a first transistor coupled to a digital control signal that adjusts a delay of the ring oscillator stage by turning on or off the transistor and a second transistor having a gate input coupled to a first or second voltage. A first plurality of the ring oscillator stages have the second transistor tied to the first voltage causing the second transistor to be on and a second plurality of the oscillator stages being tied to the second voltage causing the second transistor to be off, thus biasing the stage towards either being faster or slower, respectively.
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This application claims the benefit of provisional Application No. 60/396,500, filed Jul. 17, 2002, which application is incorporated herein by reference in its entirety.
FIELD OF THE INVENTIONThis invention relates to receivers for high-speed serial communication systems and more particularly to aspects of clock and data recovery circuits used therein.
DESCRIPTION OF THE RELATED ARTCommunication systems frequently transmit data in which the clock is embedded in the data stream rather than sent as a separate signal. When the data stream is received, a clock and data recovery circuit recovers the embedded clock and retimes the received data to the recovered clock. Traditionally, a phase-locked loop (PLL) has been used to perform the clock recovery operation. A typical phase locked loop configured for clock and data recovery operations includes a phase detector that samples the input data signal using a clock supplied by a voltage controlled oscillator (VCO). In one embodiment of a bang—bang phase detector, the phase detector determines whether the input data signal is being sampled early or late and supplies information to adjust the VCO accordingly.
In general, controlling the oscillator phase in order to accurately recover clock and data is an important aspect of successful clock and data recovery circuits. It would be desirable to provide improvements and greater flexibility in controlling the oscillator.
SUMMARYAccordingly, in one embodiment, the invention provides separate controls for each stage of a ring oscillator. By providing separate controls, each stage can be more coarsely tuned than if all stages received the same control voltage to adjust stage delay, but still provide adequate overall granularity in terms of phase adjustment for the oscillator.
In one embodiment an integrated circuit is provided that includes a ring oscillator including multiple stages. Each of the multiple stages has a stage delay that is adjustable independently of other of the multiple stages. The delay may be controlled using digital signals supplied to the stages. Each stage may receive two digital signals to control the delay with one or more outputs of the particular stage controlling which of the two digital signals is used to control the delay.
In one embodiment, the stages of the ring oscillator are biased towards either supplying a faster or slower output signal. In one embodiment, each stage of the ring oscillator includes a tail node having a gate of a first transistor coupled to a digital control signal that adjusts a delay of the ring oscillator stage by turning on or off the transistor and a second transistor having a gate input coupled to a fixed voltage, a first plurality of the ring oscillator stages having the second transistor tied to a first voltage causing the second transistor to be on and a second plurality of the oscillator stages being tied to a second voltage causing the second transistor to be off, thus biasing the stage towards either being faster or slower.
In another embodiment a method is provided that controls delay through ring oscillator stages independently to adjust a phase or frequency of one or more clocks generated by the ring oscillator. That independent control may be accomplished by supplying digital control signals to the ring oscillator stages to adjust the delay. The method may further include selecting one of at least two digital control signals to adjust delay through an oscillator stage according to one or more outputs of the oscillator stage.
The method may further include biasing each stage to be a fast stage or a slow stage by supplying a fixed voltage to a gate of a second transistor in the tail node of the ring oscillator stage, the stage being biased towards being one of a fast stage and a slow stage according to a value of the fixed voltage.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)Referring to
Referring to
The goal of a clock and data recovery circuit is to sample each bit in the center of the “data eye”, which is defined by the location of possible bit transitions. In other words, the ideal place to sample data is equidistant between zero crossing of the data. A bang—bang phase detector system samples the input data stream at twice the data rate with uniformly timed samples, and adjusts the phase of the sampling instants so that a predetermined half of the sampling instants (e.g., the odd samples) are aligned with the zero-crossings. That causes the other half of the samples (the even samples) to be aligned in the optimal part of the data eye.
The exemplary clock and data recovery circuit further includes sixteen data samplers, 230–237 (S0–S15, only eight of which are shown), which are configured to sample the data received from the limiting amplifier using clocks generated based on outputs of the ring oscillator 201 as described further herein. The outputs of the sampling circuits are logically combined by the XOR gates 240–247 (only eight of sixteen shown) to provide signals indicating whether the clock being used to sample the input data is “early” or “late”.
Turning back to
Referring now to
Note that the delay signals being supplied are being supplied digitally. It is desirable to avoid having the digital value of those delay signals changing while the output of the oscillator stage whose delay is being affected changes. Thus, the “early” or “late” signals coupled to a particular stage should be stable well before the transition of a clock signal generated by the particular oscillator stage and should remain stable through the changing edge. Note that the changing edge is typically very short compared to the duration of the oscillator period. Simulation can be used in order to find the appropriate delay control signals for each stage that are stable before the clock edge of interest generated by the particular stage. Note also that the early/late signals are only meaningful at the edges of the clock signal in a particular stage. Without a selector circuit described above, the timing margin is half the period of the VCO. However, with the selector circuit, each individual early/late signal has a timing margin of the entire period of the VCO.
In one embodiment, which can utilize the circuits illustrated in
Referring to
The inputs ZM and ZP (where M represents minus and P plus) on nodes 621 and 623 respectively, are both driven to ground during normal operation and provide a small current to keep the tail node 615 from discharging to ground. That in turn provides just enough common-mode feedback to each stage avoid common-mode instability.
In addition the inputs ZM and ZP are used to initialize the oscillator to a desired state. An even length oscillator such as the one illustrated in
In order to tune each stage individually, and to provide some common-mode stabilizing feedback, the tail node 615 for each stage needs to be isolated from the other stages and from ground. The gate of transistor 650 is coupled to a voltage input VB and acts to provide a small amount of impedance between the tail node and ground, without generating too much voltage for the current drop from the delay stage. If there were not enough impedance or it was just shorted out, there would be no means left to tune each stage independently, and the common-mode voltage of the oscillator would drift until the oscillator stopped functioning. If there were too much voltage drop, the oscillator stage might not run fast enough.
Note that the “early” outputs from the logic gate, when asserted, should cause the drive transistor 617 to be off, causing the transitions in the oscillator stage to occur more slowly and the “late” outputs from the logic gates 330–337, indicating that the sample circuit sample late, should cause the drive transistor 617 to be on, thereby causing the transitions in the oscillator stage to occur more quickly.
There are several types of bang—bang phase detectors. In one type of bang—bang phase detector, only two pieces of information are provided, speed up or slow down. In another type of bang—bang phase detector, three states are provided, speed up, slow down, or do nothing. A third state can be achieved in the embodiment illustrated in
Referring again to
Note that the sizes of transistors 660 and 662 may be varied by including additional transistors using metal mask techniques well known in the art. Usually, the transistor 650 will be much larger than transistors 617 and 625, because the bang—bang input should have a relatively small impact on the delay. Transistors 670 and 672 will generally be comparable to transistors 674 and 676. In one embodiment, transistors 678 and 682 are about ⅓ the strength of 674 and 676, but that could vary greatly in different embodiments. If transistors 678 and 678, are relatively larger, the oscillator stage runs faster but has relatively slower edges.
In the second scenario at 703, all eight stages have a delay input causing the drive transistor 617 to be off. If the fixed input alternates between ‘0’ and ‘1’ for the stages, half the stages operate with the transistor gate inputs set to ‘00’ and half to ‘01’. Those stages operating at ‘01’ are balanced and those stages operating at ‘00’ slow down. Cumulatively, the ring oscillator operates more slowly since four stages are set to run slower and four stages are set to a balanced position.
Note that the cases shown at 701 and 703 are examples with data at the extremes, and with more typical data, fewer than four stages may be tuned away from the balance point. Having fewer than four stages tuned away from the balance point still causes the VCO to speed up or slow down (depending on the direction of tuning).
Referring to the third scenario shown in
Use of the fixed transistor accounts for a small amount of skew that may be present because of the tendency of the ring oscillator to move towards its stable oscillating state. Because the stages are tuned individually, there will be some small instantaneous variation delay, and hence the clocks will not be perfectly aligned. However, that variation is negligibly small, at least in certain embodiments. Note that in some embodiments, the fixed transistor is not used.
An exemplary sampler circuit 230 is shown in more detail in
The latch 820 is shown in
The sampler circuit also includes sample and hold circuits 830 formed respectively by transistors 831 and 832 and capacitance on nodes QINT and QINT_B, which sample the data on nodes 801 and 803, respectively, when the sample pulse 803 is active. The sample pulse immediately follows the clear pulse. An active low latch pulse on node 811 causes the latch 840, formed by transistors 841, 843, 845 and 847, to latch the signal provided by sample and hold circuit 830. That also results in latch 820 receiving the sampled data.
Referring again to
In other embodiments of the invention, the sample circuit is implemented as a conventional current mode logic (CML) sampler circuit and the pulse shaper circuit is not used.
Thus, a ring oscillator having the capability to individually control the delay through each stage has been described The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For instance, while in some embodiments, all the stages may be separately controlled, in other embodiments, a group of two or more stages may be controlled by one set of delay control signals and other groups may be controlled by other sets of delay control signals. Further, while some logic has been shown as single ended and some as differential, differential logic may be utilized instead of single-ended and single-ended logic may be used instead of differential logic. Other variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.
Claims
1. An integrated circuit comprising:
- a ring oscillator including multiple stages;
- a plurality of sampling circuits coupled to the ring oscillator and coupled to sample a data signal received by the integrated circuit, respective outputs of the sampling circuits being logically combined to form digital signals utilized to control, at least in part, delay through the multiple stages of the ring oscillator; and
- wherein each of the multiple stages has a stage delay that is adjustable independently of others of the multiple stages.
2. The integrated circuit as recited in claim 1 wherein respective stages are coupled to respectively receive at least one of the digital signals to adjust a delay of the respective stage according to a value of the at least one digital signal.
3. The integrated circuit as recited in claim 2 wherein the stages receive respective first and second digital signals, the delay through respective stages being determined at any particular time according to a value of at least one of the first and second digital signals.
4. The integrated circuit as recited in claim 3 wherein the first digital signal controls delay during a first part of a period of the stage and the second digital signal controls delay during another part of the period of the stage.
5. The integrated circuit as recited in claim 3 wherein one digital signal is utilized according to a value of a first output signal of a respective stage and the second digital signal is utilized according to a value of a second output signal of the respective stage.
6. The integrated circuit as recited in claim 3 wherein each stage further includes a selector circuit coupled to receive the first and second digital signals, the selector circuit selecting one of the first and second digital signals to control the delay of each respective stage.
7. The integrated circuit as recited in claim 6 wherein the selector circuit selects one of the first and second digital signals according to one or more outputs generated by the respective stage.
8. The integrated circuit as recited in claim 3 wherein the first and second digital signals, indicate that signals used in sampling received data are one of early and late.
9. The integrated circuit as recited in claim 1 wherein each of the digital signals indicates that the data signal is being sampled one of early or late in the sampling circuits.
10. The integrated circuit as recited in claim 1 wherein each of the stages of the ring oscillator is biased towards either supplying a faster or slower output signal, a first plurality of the stages being biased towards supplying the faster output signal and a second plurality of the stages being biased towards supplying the slower output signal.
11. The integrated circuit as recited in claim 1 wherein,
- at least one stage of the ring oscillator includes a tail node having a gate of a first transistor coupled to one of the digital signals that adjusts a delay of the ring oscillator stage by turning on or off the transistor; and
- wherein the tail node of the at least one stage includes a second transistor having a gate input coupled to a fixed voltage to cause the at least one stage to be biased towards being one of faster and slower.
12. The integrated circuit as recited in claim 1 wherein each stage of the ring oscillator includes a tail node having a gate of a first transistor coupled to one of the digital signals that adjusts a delay of the ring oscillator stage by turning on or off the transistor and a second transistor having a gate input coupled to one of a first and second voltage, a first plurality of the ring oscillator stages having the second transistor tied to the first voltage causing the second transistor to be on and a second plurality of the oscillator stages being tied to the second voltage causing the second transistor to be off.
13. The integrated circuit as recited in claim 12 wherein the first and second voltages are fixed.
14. A method comprising:
- receiving a data signal;
- sampling the data signal in a plurality of sampling circuits using sampling signals generated based on outputs of a ring oscillator;
- logically combining respective outputs of the sampling circuits to form digital control signals for controlling respective delays through stages of the ring oscillator; and
- controlling delay through the ring oscillator stages independently using respective digital control signals to adjust a phase or frequency of one or more output signals generated by the ring oscillator.
15. The method as recited in claim 14 further comprising supplying respective digital control signals to each of the ring oscillator stages to adjust the delay through each ring oscillator stage independently of other ring oscillator stages according to the respective digital control signals, thereby adjusting the phase of the one or more output signals.
16. A method comprising:
- controlling delay through ring oscillator stages independently to adjust a phase or frequency of one or more output signals generated by the ring oscillator; and
- selecting one of at least two digital control signals to adjust delay through one of the ring oscillator stages according to one or more outputs of the one ring oscillator stage.
17. The method as recited in claim 14 wherein the digital control signals indicate to the oscillator stage to do one of increasing the delay and reducing the delay of the oscillator stage, thereby adjusting the phase of the one or more output signals of the ring oscillator.
18. The method as recited in claim 14 wherein a plurality of the digital control signals indicate that the data signal is being sampled early and a plurality of the digital control signals indicate that the data is being sampled late.
19. The method as recited in claim 14 further comprising biasing each of the ring oscillator stages to be biased towards supplying one of a faster and a slower output signal, a first plurality of the ring oscillator stages being biased towards supplying the faster output signal and a second plurality of the stages being biased towards supplying the slower output signal.
20. The method as recited in claim 14 further comprising adjusting a delay of a ring oscillator stage by turning on or off a first transistor in a tail node of the ring oscillator stage, using one of the digital control signals coupled to a gate the first transistor.
21. The method as recited in claim 20 further comprising selecting the digital control signal supplied to the gate from at least two digital control signals supplied to the ring oscillator stage, the two digital control signals indicating one of early or late.
22. The method as recited in claim 20 further comprising biasing each stage to be a fast stage or a slow stage by supplying a fixed voltage to a gate of a second transistor in the tail node of the ring oscillator stage, the stage being biased towards one of a fast stage and a slow stage according to a value of the fixed voltage.
23. The method as recited in claim 22 further comprising biasing a first plurality of stages to be slow stages and a second plurality of the stages to be fast stages.
24. An apparatus comprising:
- a ring oscillator including means for adjusting a delay of each ring oscillator stage independently;
- a plurality of sampling circuits coupled to the ring oscillator for sampling high speed data; and
- a plurality of logical circuits for logically combining outputs of the sampling circuits to form digital signals utilized to control, at least in part, respective delays through stages of the ring oscillator.
25. The apparatus as recited in claim 24 further comprising means for biasing a ring oscillator stage to being one of a fast stage or a slow stage.
26. The integrated circuit as recited in claim 2 wherein a first plurality of the digital signals indicate to speed up and a second plurality of the digital signals indicate to slow down.
27. The method as recited in claim 16 wherein the at least two digital signals both indicate one of sampling early and sampling late.
- Gray, C. Thomas, et al., “A Sampling Technique and Its CMOS Implementation with 1 Gb/s Bandwidth and 25 ps Resolution,” IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 340-349.
Type: Grant
Filed: Nov 25, 2002
Date of Patent: Feb 27, 2007
Assignee: Silicon Laboratories Inc. (Austin, TX)
Inventor: Vadim Gutnik (Austin, TX)
Primary Examiner: Arnold Kinkead
Attorney: Zagorin O'Brien Graham LLP
Application Number: 10/303,422
International Classification: H03B 27/00 (20060101);