Abstract: A clock circuit is provided for clocking a high-speed data communication interface. The interface has (N) lanes. The clock circuit includes a triangle wave generator, N clock generators, and N lane FIFOs. The triangle wave generator provides P phase outputs, wherein P is greater than or equal to N. Each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output. Each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal.

Abstract: A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter. The coefficient improvement module is configured to update the coefficients in the lookup table.

Abstract: A mobile terminal and its methods of use are disclosed herein. In an embodiment, a mobile terminal for enabling radio communications includes a common reference device, frequency conversion circuitry, and pilot tracking circuitry and/or signal tracking circuitry. The common reference device provides a common reference signal for frequency conversions. The frequency conversion circuitry uses the common reference signal from the common reference device to perform a frequency conversion of incoming or outgoing communications. The pilot tracking circuitry determines a frequency error based on a frequency of a received pilot signal and causes an adjustment to the frequency conversion performed by the frequency conversion circuitry based on the frequency error. The signal tracking circuitry determines a frequency error signal based on the frequency of an incoming communication signal and causes an adjustment to the frequency conversion performed by the frequency conversion circuitry based on the frequency error.

Abstract: Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement an RRM that saves both area and power for a given design and is able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to a 50% duty cycle clock.

Abstract: A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.

Abstract: A neural network operation apparatus and method are disclosed. The neural network operation apparatus may include an adder configured to perform addition of data for performing a neural network operation and main data, a first multiplexer configured to output one of an output result of the adder and the main data based on a reset signal, a second multiplexer configured to output one of the main data and a quantization result of the data based on a phase signal, and a controller configured to control the first and second multiplexers by generating the reset signal and the phase signal.

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

Abstract: This disclosure relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs and after being processed by these three modules, to pull-up or pull-down the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.

Abstract: An optical underwater communication system is disclosed which includes a first transceiver and a second transceiver, each including one or more optical sources configured to provide light activated and deactivated according to a first bit stream, one or more sensor packages each comprising a plurality of photodetectors configured to receive light from the other transceiver and, in response, provide an output voltage signal and an output current signal, a detector configured to i) convert the output voltage signal and the output current signal to pulses associated with arrival of photons, and ii) count the number of pulses based on a predetermined timing sequence, an encoder configured to encode a message to be sent into a first bit stream, and a decoder configured to decode a message received into a second bit stream.

Abstract: A frequency synthesizer employs a combination of a low divide ratio divider phase-locked loop (PLL) and a wide band, on-chip voltage-controlled oscillator (VCO). To reduce phase noise, low divide ratio phase detection is employed. By using the off-chip PLL with a bank of on-chip VCOs, the frequency synthesizer may have enhanced frequency stability and avoid having to include an acquisition circuit. A separation between the PLL and VCO may reduce integer boundary spurs (IBS) eliminating or reducing a need for a filter bank and switches reducing a complexity of the frequency synthesizer.

Abstract: In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.

Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.

Abstract: Time stamp replication within wireless networks is described. In an embodiment, a wireless station receives an input time stamp and uses this input time stamp to generate an output time stamp. The wireless station transmits the output time stamp to wireless stations in one of a number of groups which make up the wireless network. The output time stamp is generated to compensate for delays between receiving the input time stamp and transmitting the output time stamp such that output time stamp which is transmitted at a time T corresponds to the value that the input time stamp would have had if it had been received at time T (and not at a time earlier than T). This may, therefore, reduce or eliminate independent time stamp errors and jitter caused by multiple disparate systems and processes.

Abstract: Provided is a clock signal generation circuit. The clock signal generation circuit includes a control word generation circuit, an initial clock generation circuit and a spread spectrum clock generation circuit, wherein the control word generation circuit is connected to the initial clock generation circuit and the spread spectrum clock generation circuit; the initial clock generation circuit is further connected to the spread spectrum clock generation circuit.

Abstract: The present disclosure provides a switching current source circuit and a method for quickly establishing a switching current source. The switching current source circuit includes a first and a second switching current source branches connected in parallel with one end of a load. When the switching enable signal is switched, due to the charge coupling of the first and second switching current source branches, the bias voltage respectively generates bounce in the same direction as and a direction opposite to the transition direction of the switching enable signal. The two bounces cancel each other to make the current source bias voltage recover quickly when a toggle event happens. The present disclosure accelerates the establishment of current through the coupling of charges, and reduces the decoupling capacitance at the same time, thereby reducing the circuit area and saving the costs.

Abstract: A storage device is provided. The storage device includes nonvolatile memory devices provided on a printed circuit board (PCB), a connector, a storage controller and at least one first passive filter. The connector is provided in the PCB and includes connection terminals. The storage controller is provided on the PCB, communicates with an external host through the connection terminals and controls the nonvolatile memory devices. The at least one first passive filter is provided in the PCB, is connected between the connector and the storage controller, and performs an equalization on either a signal provided to the storage controller or a signal provided from the storage controller.

Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Abstract: Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines, the coordinator estimates the drift between the pair of machines based on the transit times of probes transmitted between the pair of machines as indicated by the probe records. For different loops of at least three machines in the mesh network, the coordinator calculates a loop drift error based on a sum of the estimated drifts between pairs of machines around the loop and adjusts the estimated absolute drifts of the machines based on the loop drift errors. Here, the absolute drift is defined relative to a drift of a reference machine.

Abstract: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: A method and an electronic device of correcting frame for an optical camera communication (OCC) are provided. The method includes the following steps. The optical signal is captured. The optical signal is input to a first machine learning (ML) model to obtain a missing timestamp. The optical signal and the missing timestamp are input to a second ML model to obtain a first complement frame corresponding to the missing timestamp. The first complement frame is outputted.

Abstract: A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to: detect rising edges in said bit stream; detect, separately, falling edges in said bit stream; and generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.

Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

Abstract: A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Abstract: A failure detection system for an energy network includes a radio frequency (RF) receiver adapted to be coupled with or in close proximity to the energy network, the RF receiver providing an amplitude modulated RF signal; an RF amplifier receiving the amplitude modulated RF signal and providing an amplified signal; an envelope detector receiving the amplitude modulated RF signal and providing a demodulated envelope signal; an optional algorithm implementation system receiving the demodulated envelope signal, where the optional algorithm implementation system processes the demodulated envelope signal by one or more of a Fast Fourier transform (FFT) trigger system and a phase-locked loop (PLL) trigger system; and a signature output that is the overall output signal of the failure detection system, wherein the signature output is adapted to indicate whether the energy network is experiencing partial discharge.

Abstract: Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.

Abstract: A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Abstract: A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Abstract: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Abstract: A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

Abstract: A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Abstract: A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

Abstract: An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.

Abstract: A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.

Abstract: Systems and methods for implementing a software emulation of a clock calibrated by the software based on sampling a hardware clock.

Abstract: A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

Abstract: Disclosed is a system for assisting in guiding and performing a procedure on a subject. The subject may be any appropriate subject such as inanimate object and/or an animate object. The guide and system may include various manipulable or movable members, such as robotic systems, and may be registered to selected coordinate systems.

Abstract: A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Abstract: A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

Abstract: The disclosure relates to method and system for correcting a clock skew in a slave device using a precision time protocol (PTP). The method includes determining an uplink delay and a downlink delay, based on at least two packet transactions in the PTP protocol and conducted between the slave device and a master device within a pre-defined accumulator time window. The method further includes determining a change in the uplink/downlink delay with respect to a reference uplink/downlink delay. The reference uplink/downlink delay correspond to a first pre-defined accumulator time window at a start of the slave device, or to a last pre-defined accumulator time window during a previous correction of the clock skew. The method further includes correcting the clock skew upon determining the change in the uplink delay to be about same in magnitude as and to be in opposite direction to the change in the downlink delay.

Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

Abstract: The invention relates to a device for synchronizing a periodic high frequency power signal (18) and an external reference signal (10). The device comprises a phase control circuit (100) and a digital oscillator circuit (130). The digital oscillator circuit (130) is connected to the phase control circuit (100). The digital oscillator circuit (130) comprises means for generating the periodic high frequency power signal (18) dependent on the control signal from the phase control circuit. The phase control circuit (100) is configured to determine a phase difference of the periodic high frequency power signal (18) and the external reference signal (10).

Abstract: A fluid flow meter system for monitoring fluid flow through a lumen includes a first ultrasonic transducer configured to transmit one or more versions of a transmit (TX) signal through a fluid flowing within the lumen, and a second ultrasonic transducer configured to receive one or more respective receive (RX) signals. The fluid flow meter system includes an analog-to-digital converter (ADC) configured to sample, at a first frequency, the one or more RX ultrasonic signals and a processor configured to generate a fine resolution signal based on the one or more RX ultrasonic signals. The fine resolution signal is associated with a second sampling rate higher than the first sampling rate. The processor is also configured to compute a cross-correlation signal indicative of cross-correlation between the fine resolution signal and a waveform and determine an estimated fluid flow parameter based on the computed cross-correlation signal.