Integrated circuit including cross-coupled transistors with two transistors of different type formed by same gate level structure and two transistors of different type formed by separate gate level structures
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region.
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This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/402,465, filed Mar. 11, 2009, now U.S. Pat. No. 7,956,421 and entitled “Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture,” which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/036,460, filed Mar. 13, 2008, entitled “Cross-Coupled Transistor Layouts Using Linear Gate Level Features,” and to U.S. Provisional Patent Application No. 61/042,709, filed Apr. 4, 2008, entitled “Cross-Coupled Transistor Layouts Using Linear Gate Level Features,” and to U.S. Provisional Patent Application No. 61/045,953, filed Apr. 17, 2008, entitled “Cross-Coupled Transistor Layouts Using Linear Gate Level Features,” and to U.S. Provisional Patent Application No. 61/050,136, filed May 2, 2008, entitled “Cross-Coupled Transistor Layouts Using Linear Gate Level Features.” The disclosure of each above-identified patent application is incorporated in its entirety herein by reference.
CROSS-REFERENCE TO RELATED APPLICATIONSThis application is related to each application identified in the table below. The disclosure of each application identified in the table below is incorporated herein by reference in its entirety.
A push for higher performance and smaller die size drives the semiconductor industry to reduce circuit chip area by approximately 50% every two years. The chip area reduction provides an economic benefit for migrating to newer technologies. The 50% chip area reduction is achieved by reducing the feature sizes between 25% and 30%. The reduction in feature size is enabled by improvements in manufacturing equipment and materials. For example, improvement in the lithographic process has enabled smaller feature sizes to be achieved, while improvement in chemical mechanical polishing (CMP) has in-part enabled a higher number of interconnect layers.
In the evolution of lithography, as the minimum feature size approached the wavelength of the light source used to expose the feature shapes, unintended interactions occurred between neighboring features. Today minimum feature sizes are approaching 45 nm (nanometers), while the wavelength of the light source used in the photolithography process remains at 193 nm. The difference between the minimum feature size and the wavelength of light used in the photolithography process is defined as the lithographic gap. As the lithographic gap grows, the resolution capability of the lithographic process decreases.
An interference pattern occurs as each shape on the mask interacts with the light. The interference patterns from neighboring shapes can create constructive or destructive interference. In the case of constructive interference, unwanted shapes may be inadvertently created. In the case of destructive interference, desired shapes may be inadvertently removed. In either case, a particular shape is printed in a different manner than intended, possibly causing a device failure. Correction methodologies, such as optical proximity correction (OPC), attempt to predict the impact from neighboring shapes and modify the mask such that the printed shape is fabricated as desired. The quality of the light interaction prediction is declining as process geometries shrink and as the light interactions become more complex.
In view of the foregoing, a solution is needed for managing lithographic gap issues as technology continues to progress toward smaller semiconductor device features sizes.
SUMMARYIn one embodiment, a semiconductor device is disclosed. The semiconductor device includes a substrate having a portion of the substrate formed to include a plurality of diffusion regions. The plurality of diffusion regions respectively correspond to active areas of the portion of the substrate within which one or more processes are applied to modify one or more electrical characteristics of the active areas of the portion of the substrate. The plurality of diffusion regions include a first p-type diffusion region, a second p-type diffusion region, a first n-type diffusion region, and a second n-type diffusion region. The first p-type diffusion region includes a first p-type active area electrically connected to a common node. The second p-type diffusion region includes a second p-type active area electrically connected to the common node. The first n-type diffusion region includes a first n-type active area electrically connected to the common node. The second n-type diffusion region includes a second n-type active area electrically connected to the common node.
The semiconductor device also includes a gate electrode level region formed above the portion of the substrate. The gate electrode level region includes a number of conductive features defined to extend over the substrate in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, such that a centerline of each respective originating rectangular-shaped layout feature is aligned with the first parallel direction. The number of conductive features include conductive features that respectively form a first PMOS transistor device gate electrode, a second PMOS transistor device gate electrode, a first NMOS transistor device gate electrode, and a second NMOS transistor device gate electrode.
The first PMOS transistor device gate electrode is formed to extend over the first p-type diffusion region to electrically interface with the first p-type active area and thereby form a first PMOS transistor device. The second PMOS transistor device gate electrode is formed to extend over the second p-type diffusion region to electrically interface with the second p-type active area and thereby form a second PMOS transistor device. The first NMOS transistor device gate electrode is formed to extend over the first n-type diffusion region to electrically interface with the first n-type active area and thereby form a first NMOS transistor device. The second NMOS transistor device gate electrode is formed to extend over the second n-type diffusion region to electrically interface with the second n-type active area and thereby form a second NMOS transistor device.
The first PMOS transistor device gate electrode is electrically connected to the second NMOS transistor device gate electrode. The first PMOS transistor device gate electrode is physically separate from the second NMOS transistor device gate electrode within the gate electrode level region. The second PMOS transistor device gate electrode is electrically connected to the first NMOS transistor device gate electrode. The second PMOS transistor device gate electrode is physically separate from the first NMOS transistor device gate electrode within the gate electrode level region. The first PMOS transistor device, the second PMOS transistor device, the first NMOS transistor device, and the second NMOS transistor device define a cross-coupled transistor configuration having commonly oriented gate electrodes formed from respective rectangular-shaped layout features.
Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
SRAM Bit Cell Configuration
The inverter 102 is defined in an identical manner to inverter 106. The inverter 102 include a PMOS transistor 121 and an NMOS transistor 123. The respective gates of the PMOS and NMOS transistors 121, 123 are connected together to form the input 102A of inverter 102. Also, each of PMOS and NMOS transistors 121, 123 have one of their respective terminals connected together to form the output 102B of inverter 102. A remaining terminal of PMOS transistor 121 is connected to the power supply 117. A remaining terminal of NMOS transistor 123 is connected to the ground potential 119. Therefore, PMOS and NMOS transistors 121, 123 are activated in a complementary manner. When a high logic state is present at the input 102A of the inverter 102, the NMOS transistor 123 is turned on and the PMOS transistor 121 is turned off, thereby causing a low logic state to be generated at output 102B of the inverter 102. When a low logic state is present at the input 102A of the inverter 102, the NMOS transistor 123 is turned off and the PMOS transistor 121 is turned on, thereby causing a high logic state to be generated at output 102B of the inverter 102.
Cross-Coupled Transistor Configuration
Based on the foregoing, the cross-coupled transistor configuration includes four transistors: 1) a first PMOS transistor, 2) a first NMOS transistor, 3) a second PMOS transistor, and 4) a second NMOS transistor. Furthermore, the cross-coupled transistor configuration includes three required electrical connections: 1) each of the four transistors has one of its terminals connected to a same common node, 2) gates of one PMOS transistor and one NMOS transistor are both connected to a first gate node, and 3) gates of the other PMOS transistor and the other NMOS transistor are both connected to a second gate node.
It should be understood that the cross-coupled transistor configuration of
Difference Between SRAM Bit Cell and Cross-Coupled Transistor Configurations
It should be understood that the SRAM bit cell of
With reference to the SRAM bit cell in
Restricted Gate Level Layout Architecture
The present invention implements a restricted gate level layout architecture within a portion of a semiconductor chip. For the gate level, a number of parallel virtual lines are defined to extend across the layout. These parallel virtual lines are referred to as gate electrode tracks, as they are used to index placement of gate electrodes of various transistors within the layout. In one embodiment, the parallel virtual lines which form the gate electrode tracks are defined by a perpendicular spacing therebetween equal to a specified gate electrode pitch. Therefore, placement of gate electrode segments on the gate electrode tracks corresponds to the specified gate electrode pitch. In another embodiment the gate electrode tracks are spaced at variable pitches greater than or equal to a specified gate electrode pitch.
Within the restricted gate level layout architecture, a gate level feature layout channel is defined about a given gate electrode track so as to extend between gate electrode tracks adjacent to the given gate electrode track. For example, gate level feature layout channels 301A-1 through 301E-1 are defined about gate electrode tracks 301A through 301E, respectively. It should be understood that each gate electrode track has a corresponding gate level feature layout channel. Also, for gate electrode tracks positioned adjacent to an edge of a prescribed layout space, e.g., adjacent to a cell boundary, the corresponding gate level feature layout channel extends as if there were a virtual gate electrode track outside the prescribed layout space, as illustrated by gate level feature layout channels 301A-1 and 301E-1. It should be further understood that each gate level feature layout channel is defined to extend along an entire length of its corresponding gate electrode track. Thus, each gate level feature layout channel is defined to extend across the gate level layout within the portion of the chip to which the gate level layout is associated.
Within the restricted gate level layout architecture, gate level features associated with a given gate electrode track are defined within the gate level feature layout channel associated with the given gate electrode track. A contiguous gate level feature can include both a portion which defines a gate electrode of a transistor, and a portion that does not define a gate electrode of a transistor. Thus, a contiguous gate level feature can extend over both a diffusion region and a dielectric region of an underlying chip level. In one embodiment, each portion of a gate level feature that forms a gate electrode of a transistor is positioned to be substantially centered upon a given gate electrode track. Furthermore, in this embodiment, portions of the gate level feature that do not form a gate electrode of a transistor can be positioned within the gate level feature layout channel associated with the given gate electrode track. Therefore, a given gate level feature can be defined essentially anywhere within a given gate level feature layout channel, so long as gate electrode portions of the given gate level feature are centered upon the gate electrode track corresponding to the given gate level feature layout channel, and so long as the given gate level feature complies with design rule spacing requirements relative to other gate level features in adjacent gate level layout channels. Additionally, physical contact is prohibited between gate level features defined in gate level feature layout channels that are associated with adjacent gate electrode tracks.
A gate electrode corresponds to a portion of a respective gate level feature that extends over a diffusion region, wherein the respective gate level feature is defined in its entirety within a gate level feature layout channel. Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel. As illustrated by the example gate level feature layout channels 301A-1 through 301E-1 of
Some gate level features may have one or more contact head portions defined at any number of locations along their length. A contact head portion of a given gate level feature is defined as a segment of the gate level feature having a height and a width of sufficient size to receive a gate contact structure, wherein “width” is defined across the substrate in a direction perpendicular to the gate electrode track of the given gate level feature, and wherein “height” is defined across the substrate in a direction parallel to the gate electrode track of the given gate level feature. It should be appreciated that a contact head of a gate level feature, when viewed from above, can be defined by essentially any layout shape, including a square or a rectangle. Also, depending on layout requirements and circuit design, a given contact head portion of a gate level feature may or may not have a gate contact defined thereabove.
A gate level of the various embodiments disclosed herein is defined as a restricted gate level, as discussed above. Some of the gate level features form gate electrodes of transistor devices. Others of the gate level features can form conductive segments extending between two points within the gate level. Also, others of the gate level features may be non-functional with respect to integrated circuit operation. It should be understood that the each of the gate level features, regardless of function, is defined to extend across the gate level within their respective gate level feature layout channels without physically contacting other gate level features defined with adjacent gate level feature layout channels.
In one embodiment, the gate level features are defined to provide a finite number of controlled layout shape-to-shape lithographic interactions which can be accurately predicted and optimized for in manufacturing and design processes. In this embodiment, the gate level features are defined to avoid layout shape-to-shape spatial relationships which would introduce adverse lithographic interaction within the layout that cannot be accurately predicted and mitigated with high probability. However, it should be understood that changes in direction of gate level features within their gate level layout channels are acceptable when corresponding lithographic interactions are predictable and manageable.
It should be understood that each of the gate level features, regardless of function, is defined such that no gate level feature along a given gate electrode track is configured to connect directly within the gate level to another gate level feature defined along a different gate electrode track without utilizing a non-gate level feature. Moreover, each connection between gate level features that are placed within different gate level layout channels associated with different gate electrode tracks is made through one or more non-gate level features, which may be defined in higher interconnect levels, i.e., through one or more interconnect levels above the gate level, or by way of local interconnect features at or below the gate level.
Cross-Coupled Transistor Layouts
As discussed above, the cross-coupled transistor configuration includes four transistors (2 PMOS transistors and 2 NMOS transistors). In various embodiments of the present invention, gate electrodes defined in accordance with the restricted gate level layout architecture are respectively used to form the four transistors of a cross-coupled transistor configuration layout.
The gate electrodes 401A and 407A of the first PMOS transistor 401 and first NMOS transistor 407, respectively, are electrically connected to the first gate node 491 so as to be exposed to a substantially equivalent gate electrode voltage. Similarly, the gate electrodes 403A and 405A of the second PMOS transistor 403 and second NMOS transistor 405, respectively, are electrically connected to the second gate node 493 so as to be exposed to a substantially equivalent gate electrode voltage. Also, each of the four transistors 401, 403, 405, 407 has a respective diffusion terminal electrically connected to the common output node 495.
The cross-coupled transistor layout can be implemented in a number of different ways within the restricted gate level layout architecture. In the exemplary embodiment of
It should be appreciated that although the cross-coupled transistors 401, 403, 405, 407 of
For example, the cross-coupled transistor layout of
The gate electrode tracks 450 and 456 extend in a first parallel direction. At least a portion of the first p-type diffusion region 480 and at least a portion of the second p-type diffusion region 482 are formed over a first common line of extent that extends across the substrate perpendicular to the first parallel direction of the gate electrode tracks 450 and 456. Additionally, at least a portion of the first n-type diffusion region 486 and at least a portion of the second n-type diffusion region 484 are formed over a second common line of extent that extends across the substrate perpendicular to the first parallel direction of the gate electrode tracks 450 and 456.
In another embodiment, two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.
In another embodiment, two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.
In yet another embodiment, two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.
In
Further with regard to
In one embodiment, electrical connection of the diffusion regions of the cross-coupled transistors to the common node 495 can be made using one or more local interconnect conductors defined at or below the gate level itself. This embodiment may also combine local interconnect conductors with conductors in higher levels (above the gate level) by way of contacts and/or vias to make the electrical connection of the diffusion regions of the cross-coupled transistors to the common node 495. Additionally, in various embodiments, conductive paths used to electrically connect the diffusion regions of the cross-coupled transistors to the common node 495 can be defined to traverse over essentially any area of the chip as required to accommodate a routing solution for the chip.
Also, it should be appreciated that because the n-type and p-type diffusion regions are physically separate, and because the p-type diffusion regions for the two PMOS transistors of the cross-coupled transistors can be physically separate, and because the n-type diffusion regions for the two NMOS transistors of the cross-coupled transistors can be physically separate, it is possible in various embodiments to have each of the four cross-coupled transistors disposed at arbitrary locations in the layout relative to each other. Therefore, unless necessitated by electrical performance or other layout influencing conditions, it is not required that the four cross-coupled transistors be located within a prescribed proximity to each other in the layout. Although, location of the cross-coupled transistors within a prescribed proximity to each other is not precluded, and may be desirable in certain circuit layouts.
In the exemplary embodiments disclosed herein, it should be understood that diffusion regions are not restricted in size. In other words, any given diffusion region can be sized in an arbitrary manner as required to satisfy electrical and/or layout requirements. Additionally, any given diffusion region can be shaped in an arbitrary manner as required to satisfy electrical and/or layout requirements. Also, it should be understood that the four transistors of the cross-coupled transistor configuration, as defined in accordance with the restricted gate level layout architecture, are not required to be the same size. In different embodiments, the four transistors of the cross-coupled transistor configuration can either vary in size (transistor width or transistor gate length) or have the same size, depending on the applicable electrical and/or layout requirements.
Additionally, it should be understood that the four transistors of the cross-coupled transistor configuration are not required to be placed in close proximity to each, although they may be closely placed in some embodiments. More specifically, because connections between the transistors of the cross-coupled transistor configuration can be made by routing through as least one higher interconnect level, there is freedom in placement of the four transistors of the cross-coupled transistor configuration relative to each other. Although, it should be understood that a proximity of the four transistors of the cross-coupled transistor configuration may be governed in certain embodiments by electrical and/or layout optimization requirements.
It should be appreciated that the cross-coupled transistor configurations and corresponding layouts implemented using the restricted gate level layout architecture, as described with regard to
Example Multiplexer Embodiments
Example Latch Embodiments
Exemplary Embodiments
In one embodiment, a cross-coupled transistor configuration is defined within a semiconductor chip. This embodiment is illustrated in part with regard to
It should be understood that in some embodiments, one or more of the first P channel transistor (401), the first N channel transistor (407), the second P channel transistor (403), and the second N channel transistor (405) can be respectively implemented by a number of transistors electrically connected in parallel. In this instance, the transistors that are electrically connected in parallel can be considered as one device corresponding to either of the first P channel transistor (401), the first N channel transistor (407), the second P channel transistor (403), and the second N channel transistor (405). It should be understood that electrical connection of multiple transistors in parallel to form a given transistor of the cross-coupled transistor configuration can be utilized to achieve a desired drive strength for the given transistor.
In one embodiment, each of the first (401A), second (407A), third (403A), and fourth (405A) gate electrodes is defined to extend along any of a number of gate electrode tracks, such as described with regard to
In various implementations of the above-described embodiment, such as in the exemplary layouts of
In various implementations of the above-described embodiment, such as in the exemplary layout of
In various implementations of the above-described embodiment, such as in the exemplary layouts of
In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a multiplexer having no transmission gates. This embodiment is illustrated in part with regard to
In the particular embodiments of
In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a multiplexer having one transmission gate. This embodiment is illustrated in part with regard to
In the exemplary embodiment of
In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having no transmission gates. This embodiment is illustrated in part with regard to
In the exemplary embodiments of
In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having two transmission gates. This embodiment is illustrated in part with regard to
In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having one transmission gate. This embodiment is illustrated in part with regard to
The layout of
In the illustrated embodiment, to facilitate fabrication (e.g., lithographic resolution) of the interconnect level feature 26-101, edges of the interconnect level feature 26-101 are substantially aligned with edges of neighboring interconnect level features 26-103, 26-105. However, it should be understood that other embodiments may have interconnect level features placed without regard to interconnect level feature alignment or an interconnect level grid. Additionally, in the illustrated embodiment, to facilitate fabrication (e.g., lithographic resolution), the gate contacts 26-118 and 26-120 are substantially aligned with neighboring contact features 26-122 and 26-124, respectively, such that the gate contacts are placed according to a gate contact grid. However, it should be understood that other embodiments may have gate contacts placed without regard to gate contact alignment or gate contact grid.
The gate electrode of transistor 26-102 is connected to the gate electrode of transistor 26-104 through gate contact 26-126, through interconnect level (e.g., Metal-1 level) feature 26-130, through via 26-132, through higher interconnect level (e.g., Metal-2 level) feature 26-134, through via 26-136, through interconnect level (e.g., Metal-1 level) feature 26-138, and through gate contacts 26-128. Although the illustrated embodiment of
It should be appreciated that the cross-coupled transistor layout of
In describing the cross-coupled layout embodiments illustrated in the various FIG. herein, including that of
The conductive path used to connect the diffusion regions of the cross-coupled transistors to the common output node in each of
It should be appreciated that the cross-coupled transistor layout defined using two gate contacts to connect one pair of complementary transistors and no gate contact to connect the other pair of complementary transistors can be implemented in as few as two gate electrode tracks, wherein a gate electrode track is defined as a virtual line extending across the gate level in a parallel relationship to its neighboring gate electrode tracks. These two gate electrode tracks can be located essentially anywhere in the layout with regard to each other. In other words, these two gate electrode tracks are not required to be located adjacent to each other, although such an arrangement is permitted, and in some embodiments may be desirable. The cross-coupled transistor layout embodiments of
It should be understood that the cross-coupled transistor layouts implemented within the restricted gate level layout architecture as disclosed herein can be stored in a tangible form, such as in a digital format on a computer readable medium. Also, the invention described herein can be embodied as computer readable code on a computer readable medium. The computer readable medium is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network of coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purpose, such as a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network the data maybe processed by other computers on the network, e.g., a cloud of computing resources.
The embodiments of the present invention can also be defined as a machine that transforms data from one state to another state. The data may represent an article, that can be represented as an electronic signal and electronically manipulate data. The transformed data can, in some cases, be visually depicted on a display, representing the physical object that results from the transformation of data. The transformed data can be saved to storage generally, or in particular formats that enable the construction or depiction of a physical and tangible object. In some embodiments, the manipulation can be performed by a processor. In such an example, the processor thus transforms the data from one thing to another. Still further, the methods can be processed by one or more machines or processors that can be connected over a network. Each machine can transform data from one state or thing to another, and can also process data, save data to storage, transmit data over a network, display the result, or communicate the result to another machine.
While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.
Claims
1. An integrated circuit, comprising:
- a first transistor of a first transistor type formed in part by a first gate electrode formed to extend lengthwise in a first direction, wherein the first gate electrode corresponds to a first portion of a first gate level conductive structure formed within a first gate level channel within a gate level region of the integrated circuit;
- a first transistor of a second transistor type formed in part by a second gate electrode formed to extend lengthwise in the first direction, wherein the second gate electrode corresponds to a second portion of the first gate level conductive structure, wherein the second gate electrode is substantially co-aligned with the first gate electrode along a common line of extent in the first direction;
- a second transistor of the first transistor type formed in part by a third gate electrode formed to extend lengthwise in the first direction, wherein the third gate electrode corresponds to a portion of a second gate level conductive structure formed within a second gate level channel within the gate level region of the integrated circuit;
- a second transistor of the second transistor type formed in part by a fourth gate electrode formed to extend lengthwise in the first direction, wherein the fourth gate electrode corresponds to a portion of a third gate level conductive structure formed within a third gate level channel within the gate level region of the integrated circuit,
- wherein the first and second transistors of the first transistor type are formed in part by diffusion regions of a first diffusion type, and wherein the first and second transistors of the second transistor type are formed in part by diffusion regions of a second diffusion type, and wherein the diffusion regions of the first diffusion type are physically separate from the diffusion regions of the second diffusion type,
- wherein each of the first, second, and third gate level conductive structures is defined within its corresponding gate level channel without physically contacting another gate level conductive structure defined within an adjoining gate level channel,
- wherein each of the first transistor of the first transistor type and the second transistor of the first transistor type is formed in part by a shared diffusion region of the first diffusion type,
- wherein each of the first transistor of the second transistor type and the second transistor of the second transistor type is formed in part by a shared diffusion region of the second diffusion type, and
- wherein the first gate level channel is located between the second and third gate level channels.
2. An integrated circuit as recited in claim 1, further comprising:
- a fourth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the fourth gate level conductive structure is positioned between two neighboring gate level conductive structures, wherein the fourth gate level conductive structure does not form a gate electrode of any transistor.
3. An integrated circuit as recited in claim 2, wherein a size of the fourth gate level conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of at least one of the first, second, and third gate level conductive structures as measured in the second direction.
4. An integrated circuit as recited in claim 1, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- an interconnect level region formed above the substrate region, the interconnect level region including a first linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction.
5. An integrated circuit as recited in claim 4, wherein the interconnect level region includes a second linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
6. An integrated circuit as recited in claim 5, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through one or more conductive structures that include one of the first and second linear-shaped conductive interconnect structures.
7. An integrated circuit as recited in claim 1, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- an interconnect level region formed above the substrate region, the interconnect level region including a first linear-shaped conductive interconnect structure formed to extend lengthwise in a second direction perpendicular to the first direction.
8. An integrated circuit as recited in claim 7, wherein the interconnect level region includes a second linear-shaped conductive interconnect structure formed to extend lengthwise in the second direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
9. An integrated circuit as recited in claim 8, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through one or more conductive structures that include one of the first and second linear-shaped conductive interconnect structures.
10. An integrated circuit as recited in claim 1, wherein each of the first, second, and third gate level conductive structures is linear-shaped and formed to extend lengthwise in the first direction.
11. An integrated circuit as recited in claim 10, wherein at least two of the first, second, and third gate level conductive structures has a substantially equal length as measured in the first direction.
12. An integrated circuit as recited in claim 11, wherein at least two of the first, second, and third gate level conductive structures has a substantially equal length as measured in the first direction.
13. An integrated circuit as recited in claim 12, further comprising:
- a fourth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the fourth gate level conductive structure is positioned between two neighboring gate level conductive structures, wherein the fourth gate level conductive structure does not form a gate electrode of any transistor.
14. An integrated circuit as recited in claim 13,further comprising:
- a fifth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, the fifth gate level conductive structure including a first portion that forms a gate electrode of a third transistor of the first transistor type and a second portion that forms a gate electrode of a third transistor of the second transistor type, wherein a size of the fifth gate level conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of the fourth gate level conductive structure as measured in the second direction.
15. An integrated circuit as recited in claim 1, further comprising:
- a first conductive contacting structure formed to physically connect to the first gate level conductive structure;
- a second conductive contacting structure formed to physically connect to the second gate level conductive structure; and
- a third conductive contacting structure formed to physically connect to the third gate level conductive structure,
- wherein the first conductive contacting structure is offset in the first direction from at least one of the second and third conductive contacting structures.
16. An integrated circuit as recited in claim 15, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- a plurality of interconnect level regions formed above the substrate region, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through one or more conductive interconnect structures formed in each of at least two of the plurality of interconnect level regions,
- wherein each of the plurality of interconnect level regions is part of a corresponding interconnect level of the integrated circuit, wherein any given one of the one or more conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
17. An integrated circuit as recited in claim 16, wherein each of the first, second, third, and fourth gate electrodes has a lengthwise centerline, and wherein the first, second, third, and fourth gate electrodes are positioned according to an equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the first, second, third, and fourth gate electrodes is an integer multiple of the equal centerline-to-centerline pitch.
18. An integrated circuit as recited in claim 17, wherein each of the first, second, and third gate level conductive structures is linear-shaped and formed to extend lengthwise in the first direction.
19. An integrated circuit as recited in claim 18, further comprising:
- a fourth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the fourth gate level conductive structure is positioned between two neighboring gate level conductive structures, wherein the fourth gate level conductive structure does not form a gate electrode of any transistor.
20. An integrated circuit as recited in claim 15, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- an interconnect level region formed above the substrate region to include a number of conductive interconnect structures that form part of an electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type, and wherein each conductive interconnect structure that forms part of the electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is located within the interconnect level region,
- wherein the interconnect level region is part of an interconnect level of the integrated circuit, wherein any given one of the number of conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
21. An integrated circuit as recited in claim 20, wherein each of the first, second, third, and fourth gate electrodes has a lengthwise centerline, and wherein the first, second, third, and fourth gate electrodes are positioned according to an equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the first, second, third, and fourth gate electrodes is an integer multiple of the equal centerline-to-centerline pitch.
22. An integrated circuit as recited in claim 21, wherein each of the first, second, and third gate level conductive structures is linear-shaped and formed to extend lengthwise in the first direction.
23. An integrated circuit as recited in claim 22, further comprising:
- a fourth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the fourth gate level conductive structure is positioned between two neighboring gate level conductive structures, wherein the fourth gate level conductive structure does not form a gate electrode of any transistor.
24. An integrated circuit as recited in claim 23, further comprising:
- a fifth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, the fifth gate level conductive structure including a first portion that forms a gate electrode of a third transistor of the first transistor type and a second portion that forms a gate electrode of a third transistor of the second transistor type, wherein a size of the fifth gate level conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of the fourth gate level conductive structure as measured in the second direction.
25. An integrated circuit as recited in claim 15, wherein the first conductive contacting structure is offset in the first direction from each of the second and third conductive contacting structures.
26. An integrated circuit as recited in claim 25, wherein each of the first, second, third, and fourth gate electrodes has a lengthwise centerline, and wherein the first, second, third, and fourth gate electrodes are positioned according to an equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the first, second, third, and fourth gate electrodes is an integer multiple of the equal centerline-to-centerline pitch.
27. An integrated circuit as recited in claim 26, wherein each of the first, second, and third gate level conductive structures is linear-shaped and formed to extend lengthwise in the first direction.
28. An integrated circuit as recited in claim 27, further comprising:
- a fourth gate level conductive structure formed within a corresponding gate level channel within the gate level region of the integrated circuit, wherein the fourth gate level conductive structure is positioned between two neighboring gate level conductive structures, wherein the fourth gate level conductive structure does not form a gate electrode of any transistor.
29. An integrated circuit as recited in claim 28, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- an interconnect level region formed above the substrate region to include a number of conductive interconnect structures that form part of an electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type, and wherein each conductive interconnect structure that forms part of the electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is located within the interconnect level region
- wherein the interconnect level region is part of an interconnect level of the integrated circuit, wherein any given one of the number of conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
30. An integrated circuit as recited in claim 1, wherein each of the first, second, third, and fourth gate electrodes has a lengthwise centerline, and wherein the first, second, third, and fourth gate electrodes are positioned according to an equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the first, second, third, and fourth gate electrodes is an integer multiple of the equal centerline-to-centerline pitch.
31. An integrated circuit as recited in claim 30, wherein each of the first, second, and third gate level conductive structures is linear-shaped and formed to extend lengthwise in the first direction.
32. An integrated circuit as recited in claim 31, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type.
33. An integrated circuit as recited in claim 32, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- a plurality of interconnect level regions formed above the substrate region, wherein each of the plurality of interconnect level regions is part of a corresponding interconnect level of the integrated circuit, wherein one of the plurality of interconnect level regions includes a number of conductive interconnect structures that form part of an electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type,
- wherein any given one of the number of conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
34. An integrated circuit as recited in claim 33, wherein some of the number of conductive interconnect structures within one of the plurality of interconnect level regions form an electrical connection between the second gate level conductive structure and the third gate level conductive structure.
35. An integrated circuit as recited in claim 32, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- a plurality of interconnect level regions formed above the substrate region, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through one or more conductive interconnect structures formed in each of at least two of the plurality of interconnect level regions,
- wherein each of the plurality of interconnect level regions is part of a corresponding interconnect level of the integrated circuit, wherein any given one of the one or more conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
36. An integrated circuit as recited in claim 35, wherein at least two of the first, second, and third gate level conductive structures has a substantially equal length as measured in the first direction.
37. An integrated circuit as recited in claim 32, wherein at least two of the first, second, and third gate level conductive structures has a substantially equal length as measured in the first direction.
38. An integrated circuit as recited in claim 37, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region; and
- a plurality of interconnect level regions formed above the substrate region, wherein each of the plurality of interconnect level regions is part of a corresponding interconnect level of the integrated circuit, wherein one of the plurality of interconnect level regions includes a number of conductive interconnect structures that form part of an electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type,
- wherein any given one of the number of conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
39. An integrated circuit as recited in claim 38, wherein some of the number of conductive interconnect structures within one of the plurality of interconnect level regions form an electrical connection between the second gate level conductive structure and the third gate level conductive structure.
40. An integrated circuit as recited in claim 39, further comprising:
- a first conductive contacting structure formed to physically connect to the second gate level conductive structure, wherein the second gate level conductive structure extends away from the first conductive contacting structure by a first extension distance as measured in the first direction away from the second transistor of the first transistor type; and
- a second conductive contacting structure formed to physically connect to the third gate level conductive structure, wherein the third gate level conductive structure extends away from the second conductive contacting structure by a second extension distance as measured in the first direction away from the second transistor of the second transistor type,
- wherein the first and second extension distances are different.
41. An integrated circuit as recited in claim 37, further comprising:
- a substrate region, wherein the gate level region of the integrated circuit is formed above the substrate region,
- wherein either the second gate level conductive structure includes a portion that extends over a non-diffusion area of the substrate region located between two diffusion regions of the second diffusion type, or the third gate level conductive structure includes a portion that extends over a non-diffusion area of the substrate region located between two diffusion regions of the first diffusion type, or the second gate level conductive structure includes a portion that extends over a non-diffusion area of the substrate region located between two diffusion regions of the second diffusion type and the third gate level conductive structure includes a portion that extends over a non-diffusion area of the substrate region located between two diffusion regions of the first diffusion type.
42. An integrated circuit as recited in claim 41, further comprising:
- a plurality of interconnect level regions formed above the substrate region, wherein each of the plurality of interconnect level regions is part of a corresponding interconnect level of the integrated circuit, wherein one of the plurality of interconnect level regions includes a number of conductive interconnect structures that form part of an electrical connection between the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type,
- wherein any given one of the number of conductive interconnect structures includes 1) a corresponding first connection area portion that physically connects to at least one structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, and 2) a corresponding second connection area portion that physically connects to another structure in any level of the integrated circuit different from the interconnect level that includes the given conductive interconnect structure, wherein the corresponding first connection area portion does not vertically overlap the corresponding second connection area portion relative to the substrate region.
43. An integrated circuit as recited in claim 42, wherein some of the number of conductive interconnect structures within one of the plurality of interconnect level regions form an electrical connection between the second gate level conductive structure and the third gate level conductive structure.
44. An integrated circuit as recited in claim 42, further comprising:
- a first conductive contacting structure formed to physically connect to the second gate level conductive structure, wherein the second gate level conductive structure extends away from the first conductive contacting structure by a first extension distance as measured in the first direction away from the second transistor of the first transistor type; and
- a second conductive contacting structure formed to physically connect to the third gate level conductive structure, wherein the third gate level conductive structure extends away from the second conductive contacting structure by a second extension distance as measured in the first direction away from the second transistor of the second transistor type,
- wherein the first and second extension distances are different.
45. A method for creating a layout of an integrated circuit, comprising:
- operating a computer to define a first transistor of a first transistor type formed in part by a first gate electrode formed to extend lengthwise in a first direction, wherein the first gate electrode corresponds to a first portion of a first gate level conductive structure formed within a first gate level channel within a gate level region of the integrated circuit;
- operating a computer to define a first transistor of a second transistor type formed in part by a second gate electrode formed to extend lengthwise in the first direction, wherein the second gate electrode corresponds to a second portion of the first gate level conductive structure, wherein the second gate electrode is substantially co-aligned with the first gate electrode along a common line of extent in the first direction;
- operating a computer to define a second transistor of the first transistor type formed in part by a third gate electrode formed to extend lengthwise in the first direction, wherein the third gate electrode corresponds to a portion of a second gate level conductive structure formed within a second gate level channel within the gate level region of the integrated circuit;
- operating a computer to define a second transistor of the second transistor type formed in part by a fourth gate electrode formed to extend lengthwise in the first direction, wherein the fourth gate electrode corresponds to a portion of a third gate level conductive structure formed within a third gate level channel within the gate level region of the integrated circuit,
- wherein the first and second transistors of the first transistor type are formed in part by diffusion regions of a first diffusion type, and wherein the first and second transistors of the second transistor type are formed in part by diffusion regions of a second diffusion type, and wherein the diffusion regions of the first diffusion type are physically separate from the diffusion regions of the second diffusion type,
- wherein each of the first, second, and third gate level conductive structures is defined within its corresponding gate level channel so as to not physically contact another gate level conductive structure defined within an adjoining gate level channel,
- wherein each of the first transistor of the first transistor type and the second transistor of the first transistor type is defined in part by a shared diffusion region of the first diffusion type,
- wherein each of the first transistor of the second transistor type and the second transistor of the second transistor type is defined in part by a shared diffusion region of the second diffusion type, and
- wherein the first gate level channel is located between the second and third gate level channels within the layout of the integrated circuit.
46. “A data storage device having program instructions stored”thereon for generating a layout of an integrated circuit, comprising:
- program instructions for defining a first transistor of a first transistor type formed in part by a first gate electrode formed to extend lengthwise in a first direction, wherein the first gate electrode corresponds to a first portion of a first gate level conductive structure formed within a first gate level channel within a gate level region of the integrated circuit;
- program instructions for defining a first transistor of a second transistor type formed in part by a second gate electrode formed to extend lengthwise in the first direction, wherein the second gate electrode corresponds to a second portion of the first gate level conductive structure, wherein the second gate electrode is substantially co-aligned with the first gate electrode along a common line of extent in the first direction;
- program instructions for defining a second transistor of the first transistor type formed in part by a third gate electrode formed to extend lengthwise in the first direction, wherein the third gate electrode corresponds to a portion of a second gate level conductive structure formed within a second gate level channel within the gate level region of the integrated circuit;
- program instructions for defining a second transistor of the second transistor type formed in part by a fourth gate electrode formed to extend lengthwise in the first direction, wherein the fourth gate electrode corresponds to a portion of a third gate level conductive structure formed within a third gate level channel within the gate level region of the integrated circuit,
- wherein the first and second transistors of the first transistor type are formed in part by diffusion regions of a first diffusion type, and wherein the first and second transistors of the second transistor type are formed in part by diffusion regions of a second diffusion type, and wherein the diffusion regions of the first diffusion type are physically separate from the diffusion regions of the second diffusion type,
- wherein each of the first, second, and third gate level conductive structures is defined within its corresponding gate level channel so as to not physically contact another gate level conductive structure defined within an adjoining gate level channel,
- wherein each of the first transistor of the first transistor type and the second transistor of the first transistor type is defined in part by a shared diffusion region of the first diffusion type,
- wherein each of the first transistor of the second transistor type and the second transistor of the second transistor type is defined in part by a shared diffusion region of the second diffusion type, and
- wherein the first gate level channel is located between the second and third gate level channels within the layout of the integrated circuit.
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Type: Grant
Filed: Apr 2, 2010
Date of Patent: Sep 4, 2012
Patent Publication Number: 20100187622
Assignee: Tela Innovations, Inc. (Los Gatos, CA)
Inventor: Scott T. Becker (Scotts Valley, CA)
Primary Examiner: Wensing Kuo
Attorney: Martine Penilla Group, LLP
Application Number: 12/753,795
International Classification: H01L 27/06 (20060101);