Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where processing of the device includes use of a carrier wafer.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

Abstract: A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport.

Abstract: A flash memory device includes a plurality of flash memory cell arrays, wherein: a flash memory cell array in the plurality of flash memory cell arrays comprises a plurality of layers of flash memory cell planes; and a flash memory cell plane includes a plurality of flash memory cells. The flash memory device further includes a logic circuitry coupled to the plurality of flash memory cell arrays, configured to perform operations using the plurality of flash memory cell arrays; and a sensing circuitry configured to access a corresponding flash memory cell plane among the plurality of flash memory cell planes.

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

Abstract: A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

Abstract: Proposed is an anodic oxide film structure that includes an anodic oxide film sheet and has high strength, chemical resistance and corrosion resistance.

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

Abstract: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.

Abstract: A method for distributing deep trench (DT) capacitance in an integrated circuit (IC) design is provided. The method includes forming a placement block that includes blockages defining openings in interstitial regions among the blockages, superimposing the placement block over the IC design and providing distributed DT capacitance to the IC design. The providing of the distributed DT capacitance includes adding DT capacitance cells through the openings to portions of the IC design where there are no reserved blocks.

Abstract: Provided are systems, methods, and computer products for interactive cable routing and planning optimization for customized hardware configurations. An example method includes receiving a set of cable characteristics and a set of user selections, in which the set of user selections are received via a graphical user interface (GUI). Identifying possible cabling routes for a hardware configuration based, at least in part, on available plug start and termination locations. Ranking each of the possible cabling routes based, at least in part, on a prioritized list of optimization criteria and the set of cable characteristics. Generating a suggested cabling configuration for one or more applications based, at least in part, on the set of cable characteristics, the set of user selections, and the ranking. Outputting the suggested cabling configuration to the user by at least providing a three-dimensional view of the suggested cabling configuration via the GUI.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: A control apparatus is communicably connected to a plurality of processing apparatuses, including a processor configured to determine whether the sum of an execution time of a first process, an execution time of a second process, and a time taken for a first processing apparatus among the plurality of processing apparatuses to rewrite a logic for executing the first process to a logic for executing the second process is equal to or smaller than a unit time; determine whether a data traffic between the plurality of processing apparatuses is equal to or smaller than a threshold when the first processing apparatus executes the first and second processes, and cause the first processing apparatus to execute the first and second processes when it is determined that the sum is equal to or smaller than the unit time and the data traffic is equal to or smaller than the threshold.

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

Abstract: Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.

Abstract: Systems and methods are provided for calculating a power characteristic of an integrated circuit design. For each standard cell of a gate-level netlist, a path length and a set of attributes are computed. For each leaf-level instance of a register-transfer level (RTL) netlist, a path length and a set of attributes are computed. The standard cells are partitioned into first subsets, each of the first subsets containing standard cells with a same path length and a same set of attributes. For each first subset, a relative percentage for each type of standard cell included in the first subset is calculated. The leaf-level instances are partitioned into second subsets. For each pair of corresponding first and second subsets, standard cells are associated with the leaf-level instances of the second subset based on the relative percentages. A power characteristic of the RTL netlist is calculated based on the associated standard cells.

Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.

Abstract: A method for determining a self-assembly pattern of a block copolymer confined inside a closed outline called the guiding outline, comprises the following steps, which are implemented by computer: a) choosing in a database a closed outline called the reference outline that is similar to the guiding outline, a self-assembly pattern of the block copolymer, called the reference pattern, being associated with the reference outline; b) applying a geometric transformation to a plurality of points of said reference pattern in order to convert them to respective points called image points of the self-assembly pattern to be determined. A computer program product for implementing such a method is provided.

Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

Abstract: A dynamically configurable intelligent controller of a machine tool based on DSP/FPGA and control method thereof are disclosed. The intelligent controller includes a DSP/FPGA information processing module, a data input module, an output execution module and an embedded central processing system module. The DSP/FPGA information processing module includes a hardware reconfigurable information sampling unit, a digital signal processing unit, a hardware reconfigurable algorithm unit, a hardware reconfigurable control information output execution unit and a data storage unit. The DSP/FPGA information processing module configures hardware units according to an intelligent control strategy file created based on the intelligent control needs to generate an intelligent control algorithm graph.

Abstract: The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.

Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Abstract: Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Abstract: Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Abstract: A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification.

Abstract: The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: step 1, forming a gate (21) on a substrate (1); step 2, deposing a gate isolation layer (3); step 3, deposing an oxide semiconductor layer (4) and a first photoresistor layer (5); step 4, taking the gate (21) as a mask to implement a back side expose to the first photoresistor layer (5); step 5, forming an island shaped oxide semiconductor layer (41), and removing the island shaped first photoresistor layer (51); step 6, forming an island shaped etching stopper layer (6); step 7, forming a source/a drain; step 8, deposing a protecting layer (8), a second photoresistor layer (9), and implementing gray scal exposure, development to the second photoresistor layer (9); step 9, forming a pixel electrode via (81) to implement ashing process to the second photoresistor layer (9); step 10, deposing a pixel electrode layer (10); step 11, removing the remaining second photoresistor layer (9?), and forming a pixel

Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

Abstract: The disclosure relates to technology for managing signal distribution and lab resources in design validation environments that replicate a type of communication signal a consumer can experience on a wireless provider's network. For example, the validation environment will enable engineers to test VoLTE (“Voice over Long-Term Evolution”) in an LTE (“Long-Term Evolution”) for various smart phone designs and other network-based signals from various hardware combinations and suppliers. Additionally, various embodiments of the present technology provide for an automation framework that allows for efficient management of signal distribution, resource allocation, scheduling, and more.

Abstract: Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another.

Abstract: A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected.

Abstract: A non-volatile semiconductor storage device disclosed in the embodiment has a semiconductor substrate, a first insulating film, a first charge storage film, a second insulating film, a second charge storage film, a third insulating film, and a control electrode. In this non-volatile semiconductor storage device, the first and second charge storage films comprise a metallic material, a semi-metallic material or a semiconductor material. One of the first, second, and third insulating films is a multi-layered insulating film formed by layering multiple insulating films. This non-volatile semiconductor storage device further has a film comprising of any one of an oxide film, nitride film, boride film, sulfide film, and carbide film that is in contact with one interface of the laminated insulating film and contains one type of atom selected from aluminum, boron, alkaline earth metal, and transition metal at a concentration in the range of 1E12 atoms/cm2 to 1E16 atoms/cm2.

Abstract: A method for forming a field effect power semiconductor device includes providing a semiconductor body comprising a main horizontal surface and a conductive region arranged next to the main horizontal surface, forming an insulating layer on the main horizontal surface, and etching a narrow trench through the insulating layer so that a portion of the conductive region is exposed, the narrow trench comprising, in a given vertical cross-section, a maximum horizontal extension. The method further includes forming a vertical poly-diode structure comprising a horizontally extending pn-junction. Forming the vertical poly-diode structure includes depositing a polycrystalline semiconductor layer comprising a minimum vertical thickness of at least half of the maximum horizontal extension and maskless back-etching of the polycrystalline semiconductor layer to form a polycrystalline region in the narrow trench.

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Abstract: A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.

Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second lines; a metal oxide layer that is disposed alternately with the silicon-added metal oxide layer in the first direction and that is disposed in a region between two adjacent second lines and over a corresponding one of the first lines over which the silicon-added metal oxide layer is disposed; and a silicon oxide layer that is disposed alternately with the silicon-added metal oxide layer in the second direction and that is disposed in a region between two first lines and under a corresponding one of the second lines under which the silicon-added metal oxide layer is disposed.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.