Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole.
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This application is a divisional U.S. application Ser. No. 11/418,170, filed May 4, 2006, which is a divisional of U.S. application Ser. No. 11/027,443, filed Dec. 30, 2004, now U.S. Pat. No. 7,271,482, issued Sep. 18, 2007, both of which are incorporated herein by reference in their entirety.
APPLICATIONS INCORPORATED BY REFERENCEThe present application is in a related area of subject matter as the following U.S. applications, which are incorporated herein by reference: U.S. application Ser. No. 10/879,398 entitled “Packaged Microelectronic Imagers and Methods of Packaging Microelectronic Imagers” filed Jun. 29, 2004, now U.S. Pat. No. 7,294,897; U.S. application Ser. No. 10/864,974 entitled “Packaged Microelectronic Imagers and Methods of Packaging Microelectronic Imagers” filed Jun. 10, 2004; and U.S. application Ser. No. 11/056,211 entitled “Microelectronic Workpieces and Methods for Forming Interconnects in Microelectronic Workpieces” filed Feb. 10, 2005.
TECHNICAL FIELDThe present invention relates to forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
BACKGROUNDConventional packaged microelectronic devices can include a singulated microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame, and supply voltage, signals, etc., are transmitted to and from the integrated circuit via the bond-pads. In addition to the terminals, the interposer substrate can also include ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.
Packaged microelectronic devices such as those described above are used in cellphones, pagers, personal digital assistants, computers, and many other electronic products. To meet the demand for smaller electronic products, there is a continuing drive to increase the performance of packaged microelectronic devices, while at the same time reducing the height and the surface area or “footprint” of such devices on printed circuit boards. Reducing the size of high-performance devices, however, is difficult because the sophisticated integrated circuitry of such devices requires more bond-pads, which results in larger ball-grid arrays and thus larger footprints. One technique for increasing the component density of microelectronic devices within a given footprint is to stack one device on top of another.
Forming the wire-bonds 13 in the stacked device shown in
A. Overview
The following disclosure describes several embodiments of methods for forming electrically conductive through-wafer interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects. Such interconnects electrically couple terminals or other conductive elements proximate to one side of the workpiece to conductive elements proximate to the other side of the workpiece. The following describes several embodiments of methods for forming interconnects in (1) through-holes extending through the workpiece, and (2) blind holes or vias extending to an intermediate depth in the workpiece.
One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The opening can be etched and/or cut using a laser. The method continues by applying an isolation material to at least a portion of the opening. The isolation material electrically insulates the other components in the substrate from the solder material filling the opening. The method further includes depositing a solder material into at least a portion of the opening and in electrical contact with the terminal to construct an electrically conductive interconnect in the workpiece. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole.
One embodiment of a method for constructing the interconnect includes depositing an isolation material onto the workpiece and into the opening using a pulsed layer deposition process. The method continues by depositing a barrier layer onto the workpiece and into the opening. The barrier layer protects the other components in the workpiece from the other materials in the opening (e.g., copper). The method then includes depositing a seed layer onto the workpiece and into the opening. A layer of resist is then deposited over the workpiece and an aperture is formed over the opening. A conductive layer is then deposited into the opening and over at least a portion of the seed layer to form a conductive liner in the opening. The conductive layer can act as a wetting agent for filling the opening with solder material to form the interconnect. The opening is then filled with the solder material. The layer of resist is then stripped from the workpiece and the exposed portions of the seed layer are removed using a suitable etching process.
In another embodiment, constructing the interconnect includes depositing an isolation material including a silane-based oxide material onto the workpiece and into the opening. The method then includes depositing a barrier layer onto the workpiece and into the opening. The method further includes depositing a wetting layer over at least a portion of the barrier layer. The opening is then filled with the solder material.
In still another embodiment, constructing the interconnect can include depositing a dielectric liner onto the workpiece and into the opening. The dielectric liner can include a furnace oxide or another suitable dielectric material. The method further includes depositing a conductive layer over at least a portion of the dielectric liner and depositing a wetting layer over at least a portion of the conductive layer. The opening is then filled with the solder material.
Another aspect of the invention is directed toward a microelectronic assembly including a microelectronic workpiece having a substrate with a front side and a backside. The assembly can also include a plurality of microelectronic dies on and/or in the substrate. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. The assembly can also include an opening extending at least partially through the substrate and in alignment with the terminal. An isolation material can be disposed in the opening an in contact with the substrate. In several embodiments, the isolation material includes a low temperature oxide applied using a pulsed layer deposition process. In other embodiments, the isolation material can include a silane-based oxide material or another suitable dielectric material. The assembly further includes an electrically conductive interconnect in at least a portion of the opening and in electrical contact with the terminal. The interconnect includes a solder material, such as a SnAgCu solder, a SnPb solder, a AuSn solder, a solder having another composition, and/or other suitable materials or alloys of materials having the desired conductivity. Solder balls or other external electrical contacts are subsequently attached to the interconnects at the backside of the workpiece.
Specific details of several embodiments of the invention are described below with reference to interconnects extending from a terminal proximate to the front side of a workpiece, but the methods and workpieces described below can be used for other types of interconnects within microelectronic workpieces. Several details describing structures or processes that are well known and often associated with other types of microelectronic devices are not set forth in the following description for purposes of brevity. Moreover, although the following disclosure sets forth several embodiments of the invention, several other embodiments of the invention can have different configurations or components than those described in this section. As such, it should be understood that the invention may have other embodiments with additional elements or without several of the elements described below with reference to
B. Microelectronic Workpieces Having Interconnects
The external contacts 230 shown in
The interconnects 236 enable the contact pads 234 to be on the backside 214 of the substrate 210, which provides several advantages. More specifically, the external contact pads 234 can be located on the backside 214 of the substrate 210 because the interconnects 236 shown in
C. Methods for Forming Interconnects in Microelectronic Workpieces
In one embodiment of the method 300, for example, the dielectric liner of stage 320 is formed using a pulsed layer deposition process. A barrier layer of tungsten is then applied over at least a portion of the dielectric liner. At stage 330, a layer of nickel is deposited onto the tungsten using an electroless plating process. At stage 340, the hole or via is filled with a SnAgCu solder using a vacuum reflow process.
In another embodiment of the method 300, a dielectric liner is formed using a silane-based oxide material at stage 320. A barrier layer of tungsten is then deposited over at least a portion of the dielectric liner. At stage 330, a layer of nickel is applied over the tungsten using an electroless plating process. The hole or via is filled at stage 340 with a SnPb solder.
In still another embodiment of the method 300, a dielectric liner is formed using a furnace oxide at stage 320. At stage 330, a layer of TiCI4TiN is formed on at least a portion of the furnace oxide and a layer of nickel is deposited onto the layer of TiCI4TiN using an electroplating process. At stage 340, the hole or via is filled with a SnPb solder applied using a solder wave process.
Various embodiments of the individual steps of the method 300 for forming interconnects set forth above with respect to
D. Methods for Forming Interconnects in Through-Holes
Referring to
Although laser cutting the through-hole 560 may be advantageous because the substrate 210 does not need to be patterned, etching the through-hole 560 may be easier because the slag does not need to be cleaned from the through-hole 560. Another advantage of etching the through-hole 560 is that the through-hole 560 has rounded corners, which reduce stress points within the hole so that an interconnect constructed within the hole is less susceptible to stress damage. A further advantage of using an etching process is that the front side 212 of the substrate 210 can be patterned and etched to simultaneously form a plurality of through-holes 560 aligned with corresponding terminals 232.
Referring next to
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One feature of the method described above with reference to
Another feature of the method described above in
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After forming the through-hole 660, it is cleaned to remove ablated byproducts (i.e., slag) and/or other undesirable byproducts resulting from the laser. Suitable chemical cleaning agents and processes are disclosed in U.S. patent application Ser. No. 10/879,398, which was previously incorporated by reference. The slag in the through-hole 660, however, may not be cleaned in some embodiments of this method.
Referring to
After applying the fourth dielectric layer 670, a first conductive layer 672 is deposited onto the die 220. In the illustrated embodiment, the first conductive layer 672 covers the fourth dielectric layer 670. The first conductive layer 672 is generally composed of a metal, such as TiN, but in other embodiments the first conductive layer 672 can be composed of other suitable materials known to those of skill in the art. As explained below, the first conductive layer 672 provides a seed layer for plating another layer of metal into the passage 662.
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The embodiments described above with reference to
E. Methods for Forming Interconnects in Blind Holes
Referring to
The hole 920 can alternatively be formed using a laser in addition to or in lieu of etching. If a laser is used to form all or a portion of the hole 920, it is typically cleaned using chemical cleaning agents to remove slag or other contaminants as described above with respect to
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One feature of the method described above with reference to
Another advantage of several embodiments of the method described above in
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A conductive fill material is then deposited into the blind hole 925 to form an interconnect 1050 in the die 220. The fill material can include a SnPb solder deposited into the blind hole 925 using a solder wave process. In alternative embodiments, the fill material may be a solder material having a different composition or another suitable electrically conductive material. Further, the fill material may be deposited into the blind hole 925 using other methods, such as plating processes, vapor deposition processes, or other suitable methods. The interconnect 1050 has a first end 1052 proximate to the terminal 232 and a second end 1054 at the bottom of the blind hole 925.
Referring to
After the substrate 210 is thinned to a thickness T, a third dielectric layer 1110 is applied over the backside 214 of the substrate 210. The third dielectric layer 1110 can be a polyimide material or another nonconductive material generally similar to the first and second dielectric layers 550 and 552 described above with respect to
Referring to
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The interconnect 1152 has a first end 1153 contacting the backside 1122 of the terminal 232 and a second end 1154 at the backside 214 of the substrate 210. A cap 1156 can be formed at the second end 1154 of the interconnect 1152 after depositing the fill material 1150. In one embodiment, the cap 1156 can be Ni electroplated onto the interconnect 1152. In other embodiments, the cap 1156 can be a wetting agent and/or other material. A solder ball (not shown) can then be attached to the interconnect 1152 at the backside 214 of the substrate 210 to provide an external connection to other electronic devices on the backside of the die 220.
Referring next to
In the illustrated embodiment, a plurality of solder balls 1586 are coupled to corresponding contact pads 1534 at the backside of the individual devices 1510. Accordingly, the solder balls 1586 can be used to electrically connect the first microelectronic device 1510a to the second microelectronic device 1510b. A suitable underfill material 1590 or other compound can also be used to structurally attach the microelectronic devices 1510 together in the illustrated stacked-die configuration. Additionally, the solder balls 1586 at the backside of the second device 1510b can in turn be used to electrically connect the microelectronic device 1500 to another external device or board.
One feature of the embodiments illustrated in
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Various aspects of any of the foregoing embodiments can be combined in different combinations. For example, any of the methods for forming interconnects in through-holes extending through the workpiece described above can be used to form interconnects in blind holes. Likewise, any of the methods for forming interconnects in blind holes described previously can be used to form interconnects in through-holes. Accordingly, the invention is not limited except as by the appended claims.
Claims
1. A method for forming an interconnect in electrical contact with a bond-pad on a microelectronic workpiece, the method comprising:
- forming a blind hole in the workpiece and through the bond-pad, the blind hole extending from a first exterior side of the workpiece to an intermediate depth in the workpiece;
- applying a dielectric liner to at least a portion of the blind hole, wherein the dielectric liner is applied using a pulsed layer deposition process;
- depositing a barrier layer onto the workpiece and into the blind hole over at least a portion of the dielectric liner;
- applying a wetting agent into the blind hole over at least a portion of the barrier layer;
- forming a vent in the workpiece and through the dielectric liner, barrier layer, and wetting agent, wherein the vent is in fluid communication with the blind hole, and wherein the vent extends a distance through the workpiece;
- depositing a solder material into at least a portion of the blind hole and in electrical contact with the bond-pad, wherein the solder material is deposited into a least a portion of the blind hole after forming the vent, and wherein the solder material is at least approximately completely outside of the vent; and
- removing material from a second exterior side of the workpiece to thin the workpiece and remove the vent after depositing the solder material.
2. The method of claim 1 wherein forming a blind hole comprises etching a blind hole in the workpiece.
3. The method of claim 1 wherein forming a blind hole comprises laser cutting a blind hole in the workpiece.
4. The method of claim 1 wherein depositing a solder material comprises depositing a SnAgCu solder using a vacuum reflow process.
5. The method of claim 1 wherein depositing a barrier layer comprises depositing a barrier layer including W and/or Ta.
6. The method of claim 1 wherein applying a wetting agent comprises applying Ni using an electroless plating process.
7. The method of claim 1 wherein forming the vent comprises laser cutting a hole from a second exterior side of the workpiece to the blind hole.
8. The method of claim 1 wherein forming the vent comprises etching and/or mechanically drilling a hole from a second exterior side of the workpiece to the blind hole.
9. The method of claim 1 wherein forming the vent comprises laser cutting a plurality of holes from a second exterior side of the workpiece to the blind hole.
10. The method of claim 1 wherein forming the vent comprises etching and/or mechanically drilling a plurality of holes from a second exterior side of the workpiece to the blind hole.
11. The method of claim 1, further comprising:
- depositing a temporary protective filling and/or coating into the blind hole before forming the vent; and
- removing the protective filling and/or coating after forming the vent.
12. The method of claim 1 wherein depositing a solder material comprises depositing the solder material using a vacuum reflow process, solder wave process, plating process, screen printing process, vapor deposition process, placing a pre-formed sphere of solder in the blind hole and melting the solder, and/or injecting a solder paste or molten solder into the blind hole.
13. A method for forming an interconnect in electrical contact with a terminal on a microelectronic workpiece, the method comprising:
- forming a blind hole in the workpiece and through the terminal, the blind hole extending from a front side of the workpiece to an intermediate depth in the workpiece;
- applying a dielectric liner to at least a portion of the blind hole;
- forming a vent from a back side of the workpiece to the blind hole and through the dielectric liner, wherein the vent is in fluid communication with the blind hole;
- depositing a solder fill material into at least a portion of the blind hole and in electrical contact with the terminal after forming the vent, wherein the solder fill material is at least approximately completely outside of the vent, and wherein the vent enhances the solder fill process; and
- removing material from the back side of the workpiece to remove the vent after depositing the solder fill material.
14. The method of claim 13 wherein forming the vent comprises forming an opening in the workpiece sized and positioned to allow trapped air, gases, and/or volatile solvents to flow from the blind hole to the vent when filling at least a portion of the blind hole with the solder fill material.
15. The method of claim 13 wherein forming the vent comprises forming an opening extending through the workpiece, and wherein the opening includes a first end having a first diameter at the back side of the workpiece, and a second end having a second diameter less than the first diameter at the blind hole.
16. The method of claim 13, further comprising:
- depositing a barrier layer onto the workpiece and into the blind hole over at least a portion of the dielectric liner;
- depositing a seed layer onto the workpiece and into the blind hole, wherein the seed layer is over at least a portion of the barrier layer;
- applying a layer of resist over the workpiece and forming an opening over the terminal; and
- applying a conductive layer into the blind hole and over at least a portion of the seed layer before forming the vent.
17. The method of claim 16, further comprising:
- removing the layer of resist, seed layer, and barrier layer from the at least a portion of the workpiece outside the blind hole after depositing the solder fill material; and
- removing material from the back side of the workpiece to thin the workpiece.
18. A method for forming an electrically conductive interconnect, the method comprising:
- forming a blind hole in a microelectronic workpiece and through a terminal on the workpiece, the blind hole extending from a front side of the workpiece to an intermediate depth in the workpiece;
- applying a dielectric liner to at least a portion of the blind hole;
- forming a vent from a back side of the workpiece to the blind hole and through the dielectric liner, wherein the vent is in fluid communication with the blind hole;
- depositing a conductive fill material into at least a portion of the blind hole and in electrical contact with the terminal after forming the vent, wherein the conductive fill material is at least approximately completely outside of the vent,
- wherein the vent enhances the conductive fill process and wherein an interior of the vent is configured to be approximately completely free of any conductive material; and
- removing material from the back side of the workpiece to remove the vent after depositing the conductive fill material.
19. The method of claim 18 wherein forming the vent comprises forming an opening in the workpiece sized and positioned to allow trapped air, gases, and/or volatile solvents to flow from the blind hole to the vent when filling at least a portion of the blind hole with the conductive fill material.
20. The method of claim 18 wherein forming the vent comprises forming an opening extending through the workpiece, and wherein the opening includes a first end having a first diameter at the back side of the workpiece and a second end having a second diameter less than the first diameter at the blind hole.
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Type: Grant
Filed: Sep 19, 2008
Date of Patent: Dec 15, 2015
Patent Publication Number: 20090008780
Assignee: Micron Technology, Inc. (Boise, ID)
Inventor: Kyle K. Kirby (Eagle, ID)
Primary Examiner: Robert Huber
Assistant Examiner: Eric Jones
Application Number: 12/234,426
International Classification: H01L 21/4763 (20060101); H01L 21/768 (20060101); H01L 23/48 (20060101); H01L 25/065 (20060101); H01L 25/00 (20060101);