Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.

Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.

Abstract: The present application discloses an organic light emitting diode base substrate including a support substrate and a light outcoupling layer on the support substrate for enhancing light outcoupling efficiency of an organic light emitting display substrate, the light outcoupling layer having a corrugated surface on a side of the light outcoupling layer distal to the support substrate. The light outcoupling layer including a polymer material having a gradient distribution in a direction from the corrugated surface to the support substrate.

Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.

Abstract: The present disclosure relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer to cover the gate lines; planarizing the second dielectric layer; forming an insulating buffer material layer; patterning the insulating buffer material layer to form a patterned insulating buffer layer containing multiple separate portions, each separate portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer.

Abstract: A display apparatus includes a first conductive line positioned outside a display area of a substrate. A passivation layer covers a portion of the first conductive line. A second conductive line is positioned between the display area and the first conductive line, overlapping the first connection line and including a hole. The hole of the second conductive line overlaps one of at least one opening. A passivation layer is interposed between the second conductive line and a first connection line. Overlapping areas between the first and second conductive lines outside of the display area are decreased, and thus, an occurrence of a short circuit in the display apparatus is decreased.

Abstract: Provided is a display device which has a rectangular display region with four sides. The display region includes a gate line, a signal line, a first sub-pixel electrically connected to the gate line and the signal line, and a light-emitting element included in the first sub-pixel. The gate line includes a first linear portion and a second linear portion which have vectors different in direction from each other, and the first linear portion and the second linear portion are directly connected to each other. The signal line includes a third linear portion and a fourth linear portion which have vectors different in direction from each other, and the third linear portion and the fourth linear portion are directly connected. The first to fourth linear portions are each inclined from the four sides.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Abstract: A display unit includes: a drive wire; a planarization layer covering the drive wire and having a connection hole; a relay electrode provided on the planarization layer and configured to be electrically connected to the drive wire through the connection hole; a filling member made of an insulating material and provided in the connection hole; a first partition wall made of a same material as that of the filling member and covering an end of the relay electrode; a first electrode covering the filling member and configured to be electrically connected to the relay electrode; a second electrode facing the first electrode; and a functional layer located between the first electrode and the second electrode, the functional layer including a light-emitting layer.

Abstract: In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.

Abstract: A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

Abstract: Discussed is an organic light emitting display device according to the embodiments. The organic light emitting display device includes an anode electrode in each of a plurality of pixels defined on a substrate, a bank and an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, and an auxiliary electrode connected to the cathode electrode. The auxiliary electrode is provided on the bank, thereby the auxiliary electrode is disposed on a layer different from the anode electrode.

Abstract: It was learned that in an insulation heating coil used for continuously heating a running steel sheet, the conventional insulated structure of the induction heating coil was selected focusing on the heat resistance and insulation ability of the insulation itself and cannot prevent a drop in insulation ability due to entry of fine metal particles (for example, zinc fumes) in the surroundings. Therefore, an insulated structure of induction heating coil preventing the entry of zinc fumes and other fine metal particles, not falling in strength even in a high temperature environment, and able to extend the service life of the induction coil is provided. Specifically, the surface of the induction heating coil is covered with a ceramic cloth made of alumina-silica ceramic long-fibers not containing boron and the surface of that is formed with a heat-resistant insulation layer made of a surface hardening ceramic material containing alumina or alumina-silica fine particles and alumina-silica ceramic short-fibers.

Abstract: The present specification is drawn to an organic light emitting device and a method of manufacturing the same. The organic light emitting device includes a short circuit preventing layer provided on a substrate; a first electrode provided on the short circuit preventing layer, and including two or more conductive units provided to be separated from each other; a second electrode provided opposite to the first electrode; one or more organic material layers provided between the first electrode and the second electrode; and an auxiliary electrode. The short circuit preventing layer electrically connects the auxiliary electrode and the first electrode to control the quantity of leakage current even when a short-circuit defect occurs in the conductive unit.

Abstract: An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.

Abstract: A display device has layers that are laminated. The layers includes: a display layer that has a display surface for displaying an image composed of unit pixels; a pixel electrode layer arranged to correspond to each of unit pixels; a light emitting element layer laminated on the pixel electrode layer and arranged to emit light with its luminance controlled by a current; a common electrode layer provided so as to be laminated on the light emitting element layer; and a sealing layer that seals a light emitting element. The layers include at least two layers for holding the light emitting element layer therebetween and having a microcavity structure. Diffraction gratings are formed on an interface between a first grating layer and a first organic layer and on an interface between a second grating layer and a second organic layer respectively, and consequently a viewing angle is widened.

Abstract: A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.

Abstract: Display panels and encapsulation structures are described for OLED display panels, in particular. In an embodiment, a display panel includes a gate driver in panel (GIP) region, a GIP clock region within the GIP region, a pixel area region, and a VSSEL contact region laterally between an outer edge of the GIP region and the pixel area region. In some embodiments, structures are described in which capacitive coupling with the GIP clock region can be mitigated, and overlapping inorganic layers form a barrier to moisture outside of the pixel area region.

Abstract: A method for manufacturing an organic EL apparatus includes forming an organic EL element and a mounting terminal on a substrate of an element substrate as a first substrate, forming sealing films so as to cover at least the organic EL element and the mounting terminal, adhering a sealing substrate as a second substrate with respect to the element substrate using a filler, and etching the sealing films so as to expose at least a part of the mounting terminal, in which, in the etching of the sealing films, the second substrate, which is formed with a composition which reacts with an etching gas and vaporizes, or a protective member, which covers at least a part of the second substrate, is used as a mask.