Readout circuit, solid-state imaging apparatus, and method for driving readout circuit
A readout circuit includes: an amplifier (408); and offset controllers (415 and 416) configured to set an output offset voltage of the amplifier, wherein the readout circuit operates in first and second modes, in the first mode, a first voltage, and thereafter a second voltage lower than the first voltage, are input into the amplifier, in the second mode, a third voltage, and thereafter a fourth voltage higher than the third voltage, are input into the amplifier, and the offset controller switches the output offset voltage of the amplifier, between the first and second modes.
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1. Field of the Invention
The present disclosure relates to a readout circuit, a solid-state imaging apparatus, and a method for driving a readout circuit.
2. Description of the Related Art
A CMOS image sensor and a CCD image sensor include a pixel which includes a photoelectric conversion element, and a peripheral circuit which includes a readout circuit for reading out a signal that has been generated by photoelectric conversion in the pixel. In particular, CMOS image sensors are becoming to have higher functionalities due to having various modes. For instance, there is a CMOS image sensor which can switch resolution or a read out speed. As for image sensors associated with the above, there is a CMOS image sensor in which an input voltage range of the readout circuit changes and an order of input voltages change, according to the modes.
In Japanese Patent Application Laid-Open No. 2010-74784, a solid-state imaging apparatus is described which includes a photoelectric conversion element, a resetting element for resetting the photoelectric conversion element, and a plurality of clamping capacitors for accumulating electric charges therein which have been generated in the photoelectric conversion element and then have been amplified by an amplifier unit. The solid-state imaging apparatus further includes common nodes which are provided on each of the clamping capacitors and can be connected to the clamping capacitor, a plurality of pixel selecting switches each connected between the clamping capacitor and the common node, and a clamping unit for fixing the common node to a reference voltage. The solid-state imaging apparatus further includes a sampling and holding circuit which is connected to the common node through the clamping unit, and samples and holds electric charges according to the electric charge of the common node. In a first mode, the solid-state imaging apparatus accumulates the output of the amplifier unit according to the amount of an electric charge which has been obtained through photoelectric conversion by the photoelectric conversion element, in the clamping capacitor as a photo signal, and then after the photoelectric conversion element has been reset by a resetting element, accumulates the signal to be output in response to the reset by the amplifier unit, in the clamping capacitor as a reset signal. In a second mode, after the photoelectric conversion element has been reset by the resetting element, the solid-state imaging apparatus accumulates the signal to be output in response to the reset by the amplifier unit, in the clamping capacitor as the reset signal. Next, the solid-state imaging apparatus accumulates the output of the amplifier unit according to the amount of the electric charges which has been obtained through the photoelectric conversion by the photoelectric conversion element in the clamping capacitor as the photo signal to sample and hold the reset signal and a difference between the photo signal and the reset signal.
In the configuration described in Japanese Patent Application Laid-Open No. 2010-74784, in the first mode, the reset signal is input into the clamping capacitor after the photo signal, and in the second mode, the photo signal is input into the clamping capacitor after the reset signal. Accordingly, the potentials which appear in the output of the clamping unit are also different. In the first mode, the output potential of the clamping unit when the photo signal has been input into the clamping unit shall be represented by an output potential 1, and the output potential of the clamping unit when the reset signal has been input into the clamping unit shall be represented by an output potential 2. In addition, in the second mode, the output potential of the clamping unit when the reset signal has been input into the clamping unit shall be represented by an output potential 3, and the output potential of the clamping unit when the reset signal has been input into the clamping unit shall be represented by an output potential 4. Then, the relationship of the magnitude between the output potential 1 and the output potential 2 and the relationship of the magnitude between the output potential 3 and the output potential 4 are reversed. The output potential 2 of the clamping unit in the first mode and the output potential 4 of the clamping unit in the second mode becomes an electric signal which shows the difference between the photo signal and the reset signal, and the magnitude, or the polarity of the output potential 2 and the output potential 4, is reversed.
In this case, even when a dynamic range in which the clamping unit is operated is appropriate in the first mode, the dynamic range becomes narrow in the second mode, and a sufficient dynamic range may not be available. In Japanese Patent Application Laid-Open No. 2010-74784, it is described in
According to an aspect of the present invention, a readout circuit comprises: an amplifier; and an offset controller configured to set an output offset voltage of the amplifier, wherein the readout circuit operates in first and second modes, in the first mode, the amplifier inputs a first voltage, and thereafter inputs a second voltage lower than the first voltage, in the second mode, the amplifier inputs a third voltage, and thereafter inputs a fourth voltage lower than the third voltage, and the offset controller switches the output offset voltage of the amplifier, between the first and second modes.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings.
First EmbodimentIn
Next, in a pixel reset period, a signal PRES becomes a high level, and the reset transistor 403 is turned on to reset the photo detector 402. Then, the photo detector 402 outputs a pixel reset signal. The source follower transistor 404 amplifies the pixel reset signal of the photo detector 402, and outputs the pixel reset signal Vr to the pixel signal output line 406. In a period t4, a signal PSW1 becomes a high level, and a switch 411 is turned on. Then, the input capacitor 409 is connected to the input terminal (−) of the amplifier 408, and inputs the pixel reset signal Vr to the input terminal (−) of the amplifier 408. In the output terminal of the amplifier 408, the output voltage of [−(Vr−Vs)×Cf/C0+VC0R1+Voffset1] appears. Here, Cf represents the capacitance value of the feedback capacitor 413, and C0 represents the capacitance value of each of the input capacitors 409 and 410. In a period t5, a signal PT2 becomes a high level, and a switch 418 is turned on. Then, the capacitor 420 samples and holds the voltage of [−(Vr−Vs)×Cf/C0+VC0R1+Voffset1]. After that, in a period t6, signals HSR1 and HSR2 sequentially become a high level, and switches 421 and 422 are turned on. Then, the voltages of the capacitors 419 and 420 are output to common output lines 423 and 424, respectively. An output amplifier 425 outputs a difference signal of the voltages of the common output lines 423 and 424.
Subsequently, a method for reading out the pixel signal of the pixel 401′ will be described below. In a period t7, the signal PC0R becomes a high level, and the initializing switch 414 is turned on and initializes the readout circuit 407. After that, in a period t8, the signal PT1 becomes a high level, the switch 417 is turned on, and the capacitor 419 holds the potential of [VC0R1+Voffset1] by sampling and holding. After that, in a period t9, a signal PSW2 becomes a high level, and a switch 412 is turned on. Then, in the output terminal of the amplifier 408, the output voltage of [−(Vr−Vs)×Cf/C0+VC0R1+Voffset1] appears. In a period t10, the signal PT2 becomes a high level, and the switch 418 is turned on. Then, the capacitor 420 holds the voltage of [−(Vr−Vs)×Cf/C0+VC0R1+Voffset1] by sampling and holding. After that, in a period t11, signals HSR1 and HSR2 sequentially become a high level, and switches 421 and 422 are turned on. Then, the voltages of the capacitors 419 and 420 are output to the common output lines 423 and 424, respectively. The output amplifier 425 outputs a difference signal of the voltages of the common output lines 423 and 424. In this first mode, a pixel reset noise having no correlation is contained in the photo signal Vs and the pixel reset signal Vr, and accordingly the readout circuit 407 cannot remove the pixel reset noise. For information, the pixel reset noise can be removed in a second mode which will be described later. In addition, the offset potential Voffset1 can be removed by the difference of the output amplifier 425. In such a procedure, the solid-state imaging apparatus individually reads out the signals of the pixels 401 and 401′ in time series, by using the readout circuit 407.
Next, a method will be described below as the second mode in which the readout circuit 407 adds and reads out the signals of the two pixels 401 and 401′. In the second mode, the first mode signal MODE1 becomes a low level, and the second mode signal MODE2 becomes a high level. Then, the switching device 415 outputs reference voltage VC0R2 to the input terminal (+) of the amplifier 408. In this case, the pixel reset signal Vr is first input into the readout circuit 407, and then the photo signal Vs is input which is the pixel reset signal Vr with a signal corresponding to the quantity of light superimposed thereon. Thereby, the pixel reset noise can be removed. The procedure will be described below with reference to a timing chart in
Next, in a period t4, the photo detector 402 outputs a photo signal by photoelectric conversion. The source follower transistor 404 amplifies the photo signal of the photo detector 402, and outputs the photo signal to the pixel signal output line 406. The signals PSW1 and PSW2 become a high level, and the switches 411 and 412 are turned on. Then, the input capacitors 409 and 410 are connected to the input terminal (−) of the amplifier 408. The input terminal (−) of the amplifier 408 inputs the photo signal Vs which is a blend of the photo signals of the two pixels 401 and 401′. Then, in the output terminal of the amplifier 408, the output voltage of [−(Vs−Vr)×Cf/C0+VC0R2+Voffset2] appears. In a period t5, the signal PT1 becomes a high level, and the switch 417 is turned on. Then, the capacitor 419 holds the voltage [−(Vs−Vr)×Cf/C0+VC0R2+Voffset2] by sampling and holding. After that, in a period t6, signals HSR1 and HSR2 sequentially become a high level, and switches 421 and 422 are turned on. Then, the voltages of the capacitors 419 and 420 are output to the common output lines 423 and 424, respectively. The output amplifier 425 outputs a difference signal of the voltages of the common output lines 423 and 424. The offset potential Voffset2 can be removed by the difference of the output amplifier 425. In addition, in the second mode, a pixel reset noise having correlation is contained in the photo signal Vs and the pixel reset signal Vr, and accordingly can be removed by a clamping operation of the readout circuit 407. In the second mode, the polarity of the output signal of the amplifier 408 is reversed to that in the first mode, and accordingly timings are also changed at which the output voltage of the amplifier 408 is sampled and held by the capacitors 419 and 420. Thus, the dynamic ranges of the common output lines 423 and 424 and the output amplifier 425 are controlled so as not to be suppressed.
Fall times of the signals PC0R are different between periods ta and tb in the first mode in
In the first mode, the fall periods ta and tb of the signal PC0R are extended, −ΔVa1 is decreased, the variation ΔVa1×Cf/C0 of the output of the amplifier 408 is decreased, and thereby the offset potential Voffset1 is suppressed to a low value. On the other hand, in the second mode, the fall period tc of the signal PC0R is shortened, thereby −ΔVa2 is increased, the quantity to be raised of the variation ΔVa2×Cf/C0 of the output of the amplifier 408 is increased, and the offset potential Voffset2 is increased.
In the present embodiment, the fall period of the signal PC0R is controlled and is changed between the first mode and the second mode. Specifically, a transition period of a control signal PC0R for switching the initializing switch 414 from on to off is different between the first mode and the second mode. In the second mode, the fall period tc of the signal PC0R is shortened. Thereby, the dynamic range of the output can be widened by the value of ΔVa2ΔCf/C0, and the dynamic range of the output of the amplifier 408 becomes [Vthn+ΔVa2×Cf/C0]. Thus, the dynamic range of the output can be widened. In addition, in the first mode, the fall periods to and tb of the signal PC0R are extended, and ΔVa1 may be approximated to zero. For information, the operation described here is effective in expanding the dynamic range, even in the case where signals of the pixels are not summed up in the second mode, and in the case of such a mode that only the input order of the pixel reset signal Vr and the photo signal Vs is changed which are input into the readout circuit 407.
A line sensor including one or several rows of pixels is used in an image reading apparatus in a scanner and a copying machine. In the line sensor, it is required to reduce the area of a peripheral circuit including the readout circuit. Accordingly, a rail-to-rail type operational amplifier is unsuitable for a solid-state imaging apparatus like the line sensor, because of having many numbers of elements, though having a wide dynamic range. A readout circuit which corresponds to various modes and has a wide dynamic range can be provided by expanding the dynamic range by the amplifier using the differential amplifier as in the present embodiment, without increasing the chip area. The same can be applied to subsequent embodiments.
The switching device (offset controller) 415 inputs different reference voltages VC0R1 and VC0R2 in the first mode and in the second mode, respectively, into the input terminal (+) of the differential amplifier 408.
Second EmbodimentIn the first mode, a first mode signal MODE1 becomes a high level and a second mode signal MODE2 becomes a low level, as in the timing chart in
Incidentally, the signal PC0R1 may be lowered in the periods to and tb in the first mode in
In the first mode, the first mode signal MODE1 becomes a high level, and the second mode signal MODE2 becomes a low level, as in the timing chart in
For information, it is also possible to lower the signal PC0R in the periods ta and tb in the first mode in
In the first mode, the first mode signal MODE1 becomes a high level and the second mode signal MODE2 becomes a low level, as in the timing chart in
In the second mode, the first mode signal MODE1 becomes a low level and the second mode signal MODE2 becomes a high level, as in the timing chart in
In the present embodiment, a clamp voltage of the output of the amplifier 408 is not determined by the input reference voltage VC0R, but the offset voltage VOFFSET1 or VOFFSET2 is written in the output terminal of the feedback capacitor 413, in the state in which the voltage of the amplifier is clamped. Thereby, the output offset voltage can be determined. The switching device (offset controller) 1504 applies the different offset voltages VOFFSET1 and VOFFSET2 in the first mode and the second mode, respectively, to a feedback capacitor 413, while the initializing switch 414 is turned on. In the first mode, the dynamic range can be expanded by the setting of VC0R>VOFFSET1. In the second mode, the dynamic range can be expanded by the setting of VC0R<VOFFSET2. In the first mode, the dynamic range can be expanded by the value of [VC0R−VOFFSET1] compared to the case where the output offset is determined by the input reference voltage VC0R. As well, in the second mode, the dynamic range can be expanded by the value of [VOFFSET2−VC0R].
Fifth EmbodimentIn the first mode, the first mode signal MODE1 becomes a high level and the second mode signal MODE2 becomes a low level, as in the timing chart in
In the second mode, the first mode signal MODE1 becomes a low level and the second mode signal MODE2 becomes a high level, as in the timing chart in
In the present embodiment, a clamp voltage of the output of the amplifier 1801 is not determined by the threshold voltage Vthn of the transistor 1901, but the offset voltage VOFFSET1 or VOFFSET2 is written in the output terminal of a feedback capacitor 413, in the state in which the voltage of the amplifier is clamped. Thereby, the output offset voltage can be determined. In the first mode, the dynamic range can be expanded by the setting of Vthn>VOFFSET1. In the second mode, the dynamic range can be expanded by the setting of Vthn<VOFFSET2. In the first mode, the dynamic range can be expanded by the value of [Vthn−VOFFSET1] compared to the case where the output offset is determined by the threshold voltage Vthn. As well, in the second mode, the dynamic range can be expanded by the value of [VOFFSET2−Vthn].
Note that the above embodiments are merely examples how the present invention can be practiced, and the technical scope of the present invention should not be restrictedly interpreted by the embodiments. In other words, the present invention can be practiced in various ways without departing from the technical concept or main features of the invention.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2012-156611, filed on Jul. 12, 2012, which is hereby incorporated by reference herein in its entirety.
Claims
1. A readout circuit comprising:
- an amplifier;
- an input capacitor configured to input a signal by capacitive coupling to an input terminal of the amplifier;
- an initializing switch configured to short circuit between the input terminal and an output terminal of the amplifier;
- a feedback capacitor arranged between the input terminal and the output terminal of the amplifier; and
- an offset controller configured to set an output offset voltage of the amplifier, wherein
- the readout circuit operates in first and second modes,
- in the first mode, a first voltage is input to the amplifier through the input capacitor, and thereafter a second voltage lower than the first voltage is input to the amplifier through the input capacitor,
- in the second mode, a third voltage is input to the amplifier through the input capacitor, and thereafter a fourth voltage higher than the third voltage is input to the amplifier through the input capacitor, and
- in at least one of the first mode and the second mode, after the initializing switch is turned on, the offset controller applies the output offset voltage to the output terminal of the amplifier, whereby the output offset voltage of the amplifier is set to different values between the first and second modes.
2. The readout circuit according to claim 1, wherein
- the input capacitor, the initializing switch and the feedback capacitor constitute a clamping unit configured to clamp the first voltage in the first mode, and to clamp the third voltage in the second mode.
3. The readout circuit according to claim 1, wherein
- the amplifier is a differential amplifier or a common source type amplifier.
4. The readout circuit according to claim 1, wherein
- in the first mode, after the initializing switch is turned on, the first voltage is input to the input capacitor to clamp the first voltage, and
- in the second mode, after the initializing switch is turned on, the third voltage is input to the input capacitor to clamp the third voltage.
5. The readout circuit according to claim 1, wherein
- the offset controller controls so that a transition period of a control signal for switching from on to off of the initializing switch in the first mode is different from a transition period of the control signal for switching from on to off of the initializing switch in the second mode, whereby the output offset voltage of the amplifier is set to the different values between the first and second modes.
6. The readout circuit according to claim 1, wherein
- the amplifier is a differential amplifier, and
- a reference voltage input to the differential amplifier in the first mode is different from a reference voltage input to the differential amplifier in the second mode.
7. The readout circuit according to claim 1, wherein
- a plurality of the initializing switches are provided, and
- the offset controller controls so that a number of the initializing switches turned on in the first mode is different from a number of the initializing switches turned on in the second mode, whereby the output offset voltage of the amplifier is set to the different values between the first and second modes.
8. The readout circuit according to claim 1, wherein
- the offset controller applies different offset voltages to a node on an electrical path between the feedback capacitor and the output terminal of the amplifier in an on state of the initializing switch in the first mode and in an on state of the initializing switch in the second mode, whereby the output offset voltage of the amplifier is set to the different values between the first and second modes.
9. The readout circuit according to claim 1, further comprising a second capacitor including a first terminal connected to the input terminal of the amplifier and a second terminal connected to the offset controller, wherein
- the offset controller applies different voltages to the second terminal of the second capacitor between the first and second modes, whereby the output offset voltage of the amplifier is set to different values between the first and second modes.
10. The solid-state imaging device according to claim 9, wherein
- in the first mode, a photo signal from the pixel is input to the first input terminal as the first voltage, and a pixel reset signal from the pixel is input to the first input terminal as the second voltage, and
- in the second mode, a pixel reset signal from the pixel is input to the first input terminal as the third voltage, and a photo signal from the pixel is input to the first input terminal as the fourth voltage.
11. A solid-state imaging apparatus comprising:
- a readout circuit including:
- an amplifier;
- an input capacitor configured to input a signal by capacitive coupling to an input terminal of the amplifier;
- an initializing switch configured to short circuit between the input terminal and an output terminal of the amplifier;
- a feedback capacitor arranged between the input terminal and the output terminal of the amplifier; and
- an offset controller configured to set an output offset voltage of the amplifier, wherein
- the readout circuit operates in first and second modes,
- in the first mode, a first voltage is input to the amplifier through the input capacitor, and thereafter a second voltage lower than the first voltage is input to the amplifier through the input capacitor,
- in the second mode, a third voltage is input to the amplifier through the input capacitor, and thereafter a fourth voltage higher than the third voltage is input to the amplifier through the input capacitor, and
- in at least one of the first mode and the second mode, after the initializing switch is turned on, the offset controller applies the output offset voltage to the output terminal of the amplifier, whereby the output offset voltage of the amplifier is set to different values between the first and second modes; and
- a pixel configured to generate a signal by a photoelectric conversion, wherein
- the signal generated by the pixel is input to the readout circuit.
12. The solid-state imaging apparatus according to claim 11, further comprising:
- an output amplifier configured
- to output, in the first mode, a difference between an output voltage from the amplifier at a time of inputting the first voltage and an output voltage from the amplifier at a time of inputting the second voltage, and
- to output, in the second mode, a difference between an output voltage from the amplifier at a time of inputting the third voltage and an output voltage from the amplifier at a time of inputting the fourth voltage.
13. A method of driving a readout circuit comprising an amplifier, an input capacitor configured to input a signal by capacitive coupling to an input terminal of the amplifier, an initializing switch configured to short circuit between the input terminal and an output terminal of the amplifier, a feedback capacitor arranged between the input terminal and the output terminal of the amplifier, and an offset controller configured to set an output offset voltage of the amplifier; wherein the method comprises:
- operating the readout circuit in first and second modes;
- in the first mode, inputting, to the amplifier through the input capacitor, a first voltage, and thereafter inputting a second voltage lower than the first voltage through the input capacitor;
- in the second mode, inputting, to the amplifier through the input capacitor, a third voltage, and thereafter inputting a fourth voltage higher than the third voltage through the input capacitor, and
- in at least one of the first mode and the second mode, after turning on the initializing switch, applying the output offset voltage to the output terminal of the amplifier by the offset controller, whereby the output offset voltage of the amplifier is set to different values between the first and second modes.
14. The method according to claim 13, wherein
- the input capacitor, the initializing switch and the feedback capacitor constitute a clamping unit configured to clamp the first voltage in the first mode, and to clamp the third voltage in the second mode.
15. A solid-state imaging device comprising:
- an amplifier including a first input terminal to which a signal from a pixel is input and a second input terminal to which a reference voltage is input;
- an input capacitor configured to input the signal by capacitive coupling to the first input terminal of the amplifier;
- an initializing switch configured to short circuit between the first input terminal and an output terminal of the amplifier;
- a feedback capacitor arranged between the first input terminal and the output terminal of the amplifier; and
- a switching unit configured to switch the reference voltage input to the second input terminal of the amplifier, wherein
- the solid-state imagine device operates in first and second modes, and wherein
- in the first mode a first voltage is input to the first input terminal through the input capacitor, and thereafter a second voltage lower than the first voltage is input to the first input terminal through the input capacitor;
- in the second mode a third voltage is input to the first input terminal through the input capacitor, and thereafter a fourth voltage higher than the third voltage is input to the first input terminal through the input capacitor,
- the switching unit switches the reference voltage input to the second input terminal between the first mode and the second mode, and
- in at least one of the first mode and the second mode, after the initializing switch is turned on, the output offset voltage is applied to the output terminal of the amplifier, whereby the output offset voltage of the amplifier is set to different values between the first and second modes.
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Type: Grant
Filed: Jun 17, 2013
Date of Patent: Feb 23, 2016
Patent Publication Number: 20140016007
Assignee: CANON KABUSHIKI KAISHA (Tokyo)
Inventors: Masanori Ogura (Tokyo), Hideo Kobayashi (Tokyo), Tetsunobu Kochi (Hiratsuka)
Primary Examiner: Nhan T Tran
Assistant Examiner: Chan Nguyen
Application Number: 13/919,810
International Classification: H04N 5/335 (20110101); H03F 3/45 (20060101); H04N 5/232 (20060101); H04N 5/378 (20110101);