Processor package

- Intel
Description

FIG. 1 is a perspective view of a processor package including an indented area on a surface;

FIGS. 2-4 are front, top, and back side views, respectively, of the processor package;

FIGS. 5-7 are right, left, and bottom views respectively of the processor package; and,

FIG. 8 is a cross sectional view of the processor package taken along line 8--8 in FIG. 2.

The broken lines are shown in the views for illustrative purposes only and form no part of the claimed design.

Referenced Cited
U.S. Patent Documents
D305886 February 6, 1990 Banjo et al.
D313229 December 25, 1990 Audebert et al.
D320203 September 24, 1991 Ashida
D320225 September 24, 1991 Ido et al.
D321429 November 12, 1991 Kojo
D343833 February 1, 1994 Barr et al.
D344504 February 22, 1994 Barr et al.
D344725 March 1, 1994 Barr et al.
D355414 February 14, 1995 Inoue et al.
D362846 October 3, 1995 Inoue et al.
D364861 December 5, 1995 Luong
D365556 December 26, 1995 Inoue et al.
D369352 April 30, 1996 Iwakami
D371353 July 2, 1996 Ashida et al.
D373349 September 3, 1996 Millard
D374442 October 8, 1996 Ozaki
D374665 October 15, 1996 Miyaki
D375941 November 26, 1996 Kerklaan
D376795 December 24, 1996 Ashida
D377488 January 21, 1997 Ashida
D379977 June 17, 1997 Ueda
4386388 May 31, 1983 Beun
5260601 November 9, 1993 Bandouin et al.
5528459 June 18, 1996 Ainsberry et al.
Patent History
Patent number: D398592
Type: Grant
Filed: Nov 8, 1996
Date of Patent: Sep 22, 1998
Assignee: Intel Corporation (Santa Clara, CA)
Inventor: Thomas S. Klinker (San Francisco, CA)
Primary Examiner: Freda Nunn
Law Firm: Blakely, Sokoloff, Taylor & Zafman
Application Number: 0/62,138
Classifications
Current U.S. Class: D14/114; D14/117
International Classification: 1402;