Contactor for semiconductor IC testers
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Description
FIG. 1 is a perspective view of another embodiment of FIG. 1;
FIG. 2 is a top plan view in a reduced scale of FIG. 1;
FIG. 3 is a bottom plan in a reduced scale of FIG. 1;
FIG. 4 is a front elevational view in a reduced scale of FIG. 1, the rear elevational view being a mirror image of the front elevational view;
FIG. 5 is a left side elevational view in a reduced scale of FIG. 1, the right side elevational view being a mirror image of the left side view; and,
FIG. 6 is a center horizontal cross-sectional view in an enlarged scale of FIG. 2.
Referenced Cited
Patent History
Patent number: D426522
Type: Grant
Filed: Aug 13, 1999
Date of Patent: Jun 13, 2000
Assignee: Advantest Corporation (Tokyo)
Inventor: Shigeru Matsumura (Tokyo)
Primary Examiner: Adir Aronovich
Law Firm: Christie, Parker & Hale, LLP
Application Number: 0/109,356
Type: Grant
Filed: Aug 13, 1999
Date of Patent: Jun 13, 2000
Assignee: Advantest Corporation (Tokyo)
Inventor: Shigeru Matsumura (Tokyo)
Primary Examiner: Adir Aronovich
Law Firm: Christie, Parker & Hale, LLP
Application Number: 0/109,356
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182);
Linear Array Of Identical Repeating Ports Or Contacts (i.e., In-line Array) (D13/147)
International Classification: 1303;
International Classification: 1303;