Base for a semiconductor carrier
Latest Yamaichi Electronics Co., Ltd. Patents:
Description
FIG. 1 is a top-front perspective view of a base for a semiconductor carrier of our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a bottom view thereof;
FIG. 5 is a top view thereof;
FIG. 6 is a right-end view thereof; and,
FIG. 7 is a left-end view thereof.
Claims
The ornamental design for a base for a semiconductor carrier, as shown and described.
Referenced Cited
U.S. Patent Documents
D359028 | June 6, 1995 | Siegel et al. |
5451165 | September 19, 1995 | Cearley-Cabbiness et al. |
5519332 | May 21, 1996 | Wood et al. |
5541525 | July 30, 1996 | Wood et al. |
D401567 | November 24, 1998 | Farnworth et al. |
20010043074 | November 22, 2001 | Hembree et al. |
20040016993 | January 29, 2004 | Ham et al. |
Patent History
Patent number: D525215
Type: Grant
Filed: Jun 10, 2005
Date of Patent: Jul 18, 2006
Assignee: Yamaichi Electronics Co., Ltd. (Tokyo)
Inventors: Minoru Hisaishi (Tokyo), Noriyuki Matsuoka (Tokyo), Takeyuki Suzuki (Tokyo)
Primary Examiner: Prabhakar Deshmukh
Assistant Examiner: Selina Sikder
Attorney: Finnegan, Henderson, Farabow, Garrett and Dunner, LLP
Application Number: 29/231,789
Type: Grant
Filed: Jun 10, 2005
Date of Patent: Jul 18, 2006
Assignee: Yamaichi Electronics Co., Ltd. (Tokyo)
Inventors: Minoru Hisaishi (Tokyo), Noriyuki Matsuoka (Tokyo), Takeyuki Suzuki (Tokyo)
Primary Examiner: Prabhakar Deshmukh
Assistant Examiner: Selina Sikder
Attorney: Finnegan, Henderson, Farabow, Garrett and Dunner, LLP
Application Number: 29/231,789
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)